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https://gitlab.eurecom.fr/oai/openairinterface5g.git
synced 2026-07-13 04:30:28 +00:00
[FHI72] Handle long PRACH format
Only static long PRACH configuration verified, i.e. PRACH C-plane is ignored by the RU. Note: Introducing `N_ZC` and `num_prbu` parameters is needed for testing with xran F release. However, in the K release, this information is stored in xran_rx_packet_ctl struct.
This commit is contained in:
Teodora Vladić
@@ -563,6 +563,15 @@ flexran_prach_workaround=disabled
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dl_tuning_special_slot=0x13b6
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```
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In addition, PRACH format 0 is also verified with FW v2.0.5. An example gNB config file can be found at [`gnb.sa.band77.273prb.fhi72.2x2-benetel550-long-prach.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band77.273prb.fhi72.2x2-benetel550-long-prach.conf). On the RU side, the following parameters shall be modified:
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```bash
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mimo_mode=1_3
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prach_format=long
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prach_freq_offset_dynamic=false
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lf_prach_compression_enable=true
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lf_prach_slot_id=0
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```
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#### LITEON
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The OAI configuration file [`gnb.sa.band78.273prb.fhi72.4x4-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.273prb.fhi72.4x4-liteon.conf) corresponds to:
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@@ -178,6 +178,16 @@ static int read_prach_data(ru_info_t *ru, int frame, int slot)
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struct xran_fh_config *fh_cfg = get_xran_fh_config(0);
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nr_prach_info_t prach_info = get_prach_info(0);
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uint16_t N_ZC, num_prbu;
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if ((prach_info.format & 0xff) < 4) {
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N_ZC = 839;
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num_prbu = 70;
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prach_info.N_dur = 1;
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} else {
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N_ZC = 139;
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num_prbu = 12;
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}
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int prach_start_sym = prach_info.start_symbol;
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int prach_end_sym = prach_info.N_dur + prach_start_sym;
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struct xran_ru_config *ru_conf = &fh_cfg->ru_conf;
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@@ -198,25 +208,25 @@ static int read_prach_data(ru_info_t *ru, int frame, int slot)
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/* convert Network order to host order */
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if (ru_conf->compMeth_PRACH == XRAN_COMPMETHOD_NONE) {
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if (sym_idx == prach_start_sym) {
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for (idx = 0; idx < 139 * 2; idx++) {
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for (idx = 0; idx < N_ZC * 2; idx++) {
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dst[idx] = ((int16_t)ntohs(src[idx + g_kbar]));
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}
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} else {
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for (idx = 0; idx < 139 * 2; idx++) {
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for (idx = 0; idx < N_ZC * 2; idx++) {
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dst[idx] += ((int16_t)ntohs(src[idx + g_kbar]));
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}
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}
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} else if (ru_conf->compMeth_PRACH == XRAN_COMPMETHOD_BLKFLOAT) {
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int16_t local_dst[12 * 2 * N_SC_PER_PRB] __attribute__((aligned(64)));
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int16_t local_dst[num_prbu * 2 * N_SC_PER_PRB] __attribute__((aligned(64)));
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#if defined(__i386__) || defined(__x86_64__)
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struct xranlib_decompress_request bfp_decom_req = {};
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struct xranlib_decompress_response bfp_decom_rsp = {};
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int payload_len = (3 * ru_conf->iqWidth_PRACH + 1) * 12; // 12 = closest number of PRBs to 139 REs
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int payload_len = (3 * ru_conf->iqWidth_PRACH + 1) * num_prbu;
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bfp_decom_req.data_in = (int8_t *)src;
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bfp_decom_req.numRBs = 12; // closest number of PRBs to 139 REs
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bfp_decom_req.numRBs = num_prbu;
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bfp_decom_req.len = payload_len;
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bfp_decom_req.compMethod = XRAN_COMPMETHOD_BLKFLOAT;
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bfp_decom_req.iqWidth = ru_conf->iqWidth_PRACH;
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@@ -225,16 +235,15 @@ static int read_prach_data(ru_info_t *ru, int frame, int slot)
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bfp_decom_rsp.len = 0;
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xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp);
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#elif defined(__arm__) || defined(__aarch64__)
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armral_bfp_decompression(ru_conf->iqWidth_PRACH, 12, (int8_t *)src, (int16_t *)local_dst);
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armral_bfp_decompression(ru_conf->iqWidth_PRACH, num_prbu, (int8_t *)src, (int16_t *)local_dst);
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#else
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AssertFatal(1 == 0, "BFP decompression not supported on this architecture");
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#endif
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// note: this is hardwired for 139 point PRACH sequence, kbar=2
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if (sym_idx == prach_start_sym)
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for (idx = 0; idx < (139 * 2); idx++)
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for (idx = 0; idx < (N_ZC * 2); idx++)
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dst[idx] = local_dst[idx + g_kbar];
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else
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for (idx = 0; idx < (139 * 2); idx++)
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for (idx = 0; idx < (N_ZC * 2); idx++)
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dst[idx] += (local_dst[idx + g_kbar]);
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} // COMPMETHOD_BLKFLOAT
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} // aa
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@@ -0,0 +1,273 @@
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Active_gNBs = ( "gNB-OAI");
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# Asn1_verbosity, choice in: none, info, annoying
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Asn1_verbosity = "none";
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gNBs =
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(
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{
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////////// Identification parameters:
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gNB_ID = 0xe00;
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gNB_name = "gNB-OAI";
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// Tracking area code, 0x0000 and 0xfffe are reserved values
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tracking_area_code = 1;
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plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ( { sst = 1; }); });
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nr_cellid = 1;
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////////// Physical parameters:
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pdsch_AntennaPorts_XP = 2;
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pdsch_AntennaPorts_N1 = 1;
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maxMIMO_layers = 2;
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pusch_AntennaPorts = 2;
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do_CSIRS = 1;
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do_SRS = 0;
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servingCellConfigCommon = (
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{
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#spCellConfigCommon
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physCellId = 0;
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# n_TimingAdvanceOffset = 0;
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# downlinkConfigCommon
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#frequencyInfoDL
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# center frequency = 3950.4 MHz
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# selected SSB frequency = 3950.4 MHz
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absoluteFrequencySSB = 663360;
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dl_frequencyBand = 77;
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# frequency point A = 3901.26 MHz
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dl_absoluteFrequencyPointA = 660084;
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#scs-SpecificCarrierList
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dl_offstToCarrier = 0;
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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dl_subcarrierSpacing = 1;
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dl_carrierBandwidth = 273;
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#initialDownlinkBWP
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#genericParameters
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initialDLBWPlocationAndBandwidth = 1099; #38.101-1 Table 5.3.2-1
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#
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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initialDLBWPsubcarrierSpacing = 1;
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#pdcch-ConfigCommon
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initialDLBWPcontrolResourceSetZero = 11;
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initialDLBWPsearchSpaceZero = 0;
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#uplinkConfigCommon
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#frequencyInfoUL
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ul_frequencyBand = 77;
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#scs-SpecificCarrierList
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ul_offstToCarrier = 0;
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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ul_subcarrierSpacing = 1;
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ul_carrierBandwidth = 273;
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pMax = 23;
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#initialUplinkBWP
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#genericParameters
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initialULBWPlocationAndBandwidth = 1099;
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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initialULBWPsubcarrierSpacing = 1;
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#rach-ConfigCommon
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#rach-ConfigGeneric
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prach_ConfigurationIndex = 7;
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#prach_msg1_FDM
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#0 = one, 1=two, 2=four, 3=eight
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prach_msg1_FDM = 0;
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prach_msg1_FrequencyStart = 0;
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zeroCorrelationZoneConfig = 0;
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preambleReceivedTargetPower = -100;
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#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
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preambleTransMax = 8;
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#powerRampingStep
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# 0=dB0,1=dB2,2=dB4,3=dB6
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powerRampingStep = 3;
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#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
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#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
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ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
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#one (0..15) 4,8,12,16,...60,64
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ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
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#ra_ContentionResolutionTimer
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#(0..7) 8,16,24,32,40,48,56,64
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ra_ContentionResolutionTimer = 7;
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rsrp_ThresholdSSB = 19;
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#prach-RootSequenceIndex_PR
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#1 = 839, 2 = 139
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prach_RootSequenceIndex_PR = 1;
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prach_RootSequenceIndex = 1;
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# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
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#
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# msg1_SubcarrierSpacing = 1,
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# restrictedSetConfig
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# 0=unrestricted, 1=restricted type A, 2=restricted type B
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restrictedSetConfig = 0,
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# this is the offset between the last PRACH preamble power and the Msg3 PUSCH, 2 times the field value in dB
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msg3_DeltaPreamble = 2;
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p0_NominalWithGrant = -96;
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# pucch-ConfigCommon setup :
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# pucchGroupHopping
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# 0 = neither, 1= group hopping, 2=sequence hopping
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pucchGroupHopping = 0;
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hoppingId = 0;
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p0_nominal = -96;
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ssb_PositionsInBurst_Bitmap = 0x1;
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# ssb_periodicityServingCell
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# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
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ssb_periodicityServingCell = 2;
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# dmrs_TypeA_position
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# 0 = pos2, 1 = pos3
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dmrs_TypeA_Position = 0;
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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subcarrierSpacing = 1;
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#tdd-UL-DL-ConfigurationCommon
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# subcarrierSpacing
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# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
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referenceSubcarrierSpacing = 1;
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# pattern1
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# dl_UL_TransmissionPeriodicity
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# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
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dl_UL_TransmissionPeriodicity = 6;
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nrofDownlinkSlots = 7;
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nrofDownlinkSymbols = 6;
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nrofUplinkSlots = 2;
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nrofUplinkSymbols = 4;
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ssPBCH_BlockPower = -15;
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}
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);
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# ------- SCTP definitions
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SCTP :
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{
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# Number of streams to use in input/output
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SCTP_INSTREAMS = 2;
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SCTP_OUTSTREAMS = 2;
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};
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////////// AMF parameters:
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amf_ip_address = ({ ipv4 = "172.21.6.5";});
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NETWORK_INTERFACES :
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{
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GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.130";
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GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.130";
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GNB_PORT_FOR_S1U = 2152; # Spec 2152
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};
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}
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);
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MACRLCs = (
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{
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num_cc = 1;
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tr_s_preference = "local_L1";
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tr_n_preference = "local_RRC";
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pusch_TargetSNRx10 = 180;
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pucch_TargetSNRx10 = 180;
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# dl_bler_target_upper = .35;
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# dl_bler_target_lower = .15;
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# ul_bler_target_upper = .35;
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# ul_bler_target_lower = .15;
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pusch_FailureThres = 100;
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ul_max_mcs = 28;
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}
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);
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L1s = (
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{
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num_cc = 1;
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tr_n_preference = "local_mac";
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prach_dtx_threshold = 100;
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pucch0_dtx_threshold = 10;
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pusch_dtx_threshold = 10;
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max_ldpc_iterations = 15;
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tx_amp_backoff_dB = 12; # needs to match O-RU configuration
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L1_rx_thread_core = 6;
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L1_tx_thread_core = 7;
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phase_compensation = 0; # needs to match O-RU configuration
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}
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);
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RUs = (
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{
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local_rf = "no";
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nb_tx = 2;
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nb_rx = 2;
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att_tx = 0;
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att_rx = 0;
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bands = [77];
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max_pdschReferenceSignalPower = -27;
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max_rxgain = 75;
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sf_extension = 0;
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eNB_instances = [0];
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ru_thread_core = 8;
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sl_ahead = 5;
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tr_preference = "raw_if4p5"; # important: activate FHI7.2
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do_precoding = 0; # needs to match O-RU configuration
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}
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);
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security = {
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# preferred ciphering algorithms
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# the first one of the list that an UE supports in chosen
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# valid values: nea0, nea1, nea2, nea3
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ciphering_algorithms = ( "nea0" );
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# preferred integrity algorithms
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# the first one of the list that an UE supports in chosen
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# valid values: nia0, nia1, nia2, nia3
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integrity_algorithms = ( "nia2", "nia0" );
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# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
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# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
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drb_ciphering = "yes";
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drb_integrity = "no";
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};
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log_config :
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{
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global_log_level = "info";
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hw_log_level = "info";
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phy_log_level = "info";
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mac_log_level = "info";
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rlc_log_level = "info";
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pdcp_log_level = "info";
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rrc_log_level = "info";
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ngap_log_level = "info";
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f1ap_log_level = "info";
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};
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fhi_72 = {
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dpdk_devices = ("0000:6f:01.0");
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system_core = 9;
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io_core = 10;
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worker_cores = (11);
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ru_addr = ("8c:1f:64:d1:11:1e");
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mtu = 9216;
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fh_config = ({
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T1a_cp_dl = (419, 470);
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T1a_cp_ul = (285, 336);
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T1a_up = (294, 345);
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Ta4 = (0, 831);
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ru_config = {
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iq_width = 9;
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iq_width_prach = 9;
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};
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prach_config = {
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eAxC_offset = 8;
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};
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});
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};
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