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develop

70508ebaf5 · Merge remote-tracking branch 'origin/integration_2026_w28' into develop · Updated 2026-07-10 17:05:22 +00:00
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Branches

dragonwing-build

8e42e5ac1e · feat: configurable VTCM for Hexagon LDPC skel via LDPC_HEX_VTCM cmake option · Updated 2026-06-10 07:04:05 +00:00    yigid

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gNB_TX_optim_clean

3b7b75a8e2 · CMake: enable +crypto for Cortex-A72 to get hardware PMULL for CRC · Updated 2026-06-07 21:21:51 +00:00    yigid

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fhi72-improv

f1c8e7d3f1 · WIP: Remove PUxCH/SRS queue · Updated 2026-06-05 16:12:36 +00:00    yigid

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feature/cnproc-twopass

84119947bd · TODO: verify + commit msg · Updated 2026-06-05 13:52:57 +00:00    yigid

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improv_uci_on_pusch

8622165baa · fix for CSIp1 UCI on PUSCH mapping · Updated 2026-06-05 13:51:26 +00:00    yigid

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nr-paging

8c11d04122 · doc: update FEATURE_SET.md, 5Gnas.md, rrc-dev.md · Updated 2026-06-04 18:37:55 +00:00    yigid

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issue-963

80cdc4d763 · NAS: refactor Identity Request handler and enforce spec-compliant security checks · Updated 2026-06-04 11:42:14 +00:00    yigid

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ul_mu_mimo_groups

7f741cff89 · Adding test cases for nr_ulsim_mu_mimo · Updated 2026-06-04 07:57:06 +00:00    yigid

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test-oc1

519d5b661a · remove rx timestamp alignment to 32, add second barrier before tx: txHfull and tx < rx + max_ahead · Updated 2026-06-03 13:47:57 +00:00    yigid

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test_aperiodic_srs

f1651b9162 · testing other Aerial and UL heavy conf files with aperiodic to see the CI results · Updated 2026-06-03 10:25:19 +00:00    yigid

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NR_gNB_DLSCH_CSI_RM

91665cf51c · fixes in DLSCH RB extraction · Updated 2026-06-02 14:32:49 +00:00    yigid

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remove-xran-f

cf7990b55a · Remove support for xran F release · Updated 2026-06-02 13:07:23 +00:00    yigid

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sidelink-basic-integration

4713fc622a · fix warnings · Updated 2026-06-02 12:44:56 +00:00    yigid

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f1-nrdc

bf91b249fb · NR-DC: add documentation · Updated 2026-06-02 11:11:37 +00:00    yigid

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nrppa_mac_and_rrc_procedures

258c22da60 · Add NRPPA call flow for UL-TDOA positioning · Updated 2026-06-02 09:45:52 +00:00    yigid

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multi-ue-one-interface

2987a87a52 · change datamodel in nr-ue-ru.c to implement the current status: a ru has 0 or 1 cell, a cell has 0 or 1 UE · Updated 2026-06-01 16:40:14 +00:00    yigid

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ldpc_cuda

ade2038a9c · channel_output · Updated 2026-06-01 14:03:03 +00:00    yigid

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PolarShareLib

844658ad0b · coding: replace UE pointer with polar interface · Updated 2026-06-01 13:30:20 +00:00    yigid

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fix_3870

f63b57388e · fix CSI-RS slot determination according to SSB index · Updated 2026-05-30 08:22:49 +00:00    yigid

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rework_initial_BWP

5774870122 · set 1st active bwp in dlsim and ulsim · Updated 2026-05-30 08:03:34 +00:00    yigid

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