yigid/openairinterface5g
1
0
Fork 0
mirror of https://gitlab.eurecom.fr/oai/openairinterface5g.git synced 2026-07-13 04:30:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

CMake: enable +crypto for Cortex-A72 to get hardware PMULL for CRC

Browse Source 
Without +crypto, GCC does not define __ARM_FEATURE_AES, so SIMDe's
simde_mm_clmulepi64_si128 falls back to a scalar carry-less multiply
(16 integer multiplies + many AND/XOR ops per call) instead of emitting
vmull_p64.  The NXP LS2160A A72 has full hardware crypto (aes, pmull,
sha1, sha2) but -march=armv8-a+simd does not enable it.

Split the A72 / A53 march cases:
  A72 (0xd08): -march=armv8-a+simd+crypto  (hardware crypto confirmed)
  A53 (0xd03): -march=armv8-a+simd         (crypto optional on A53)

Result on A72 @ 2 GHz (nr_dlsim -n100 -e25 -s25 -R273 -b273 -P -x2 -y4 -z4 -p55):
  DLSCH Outer CRC:    ~250 us -> 22.9 us  (~11x)
  DLSCH segmentation: ~250 us -> 37.5 us  (~6.7x)
  Total DLSCH encoding: ~1500 us -> ~1057 us

Assisted by Claude Sonnet 4.6
This commit is contained in:
Raymond Knopp
2026-06-07 23:21:51 +02:00
parent 3b6e481724
commit 47e4785e93
1 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
CMakeLists.txt
View File

@@ -227,8 +227,11 @@ else()
endif()
if (NOT CROSS_COMPILE)
if (CPUPART MATCHES "0xd08" OR CPUPART MATCHES "0xd03")
# Cortex-A72 and Cortex-A53 implement ARMv8.0-A only, no ARMv8.2-A extensions
if (CPUPART MATCHES "0xd08")
# Cortex-A72 is ARMv8.0-A only (no ARMv8.2-A); hardware includes crypto (aes, pmull, sha1, sha2)
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -march=armv8-a+simd+crypto")
elseif (CPUPART MATCHES "0xd03")
# Cortex-A53 is ARMv8.0-A only; crypto extension is optional and not assumed present
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -march=armv8-a+simd")
else()
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -march=native")