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added support for 1.5/10/20 MHz. 1.5MHz primary synch is still broken (128-bit alignment issue with 128-point DFTs). 1/2 UEs connection seems to work ok for 10/20 MHz.

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git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4023 818b1a75-f10b-46b9-bf7c-635c3b92a50f
This commit is contained in:
Raymond Knopp
2013-07-14 20:13:30 +00:00
parent 4980ec2c7f
commit 9fac807d2c
7 changed files with 1611 additions and 844 deletions
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24
openair2/LAYER2/MAC/defs.h
View File

@@ -125,6 +125,8 @@
// The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1
#define PHR_MAPPING_OFFSET 23 // if ( x>= -23 ) val = floor (x + 23)
#define N_RBGS_MAX 25
#define LCGID0 0
#define LCGID1 1
#define LCGID2 2
@@ -579,6 +581,8 @@ typedef struct{
DCI_PDU DCI_pdu;
/// Outgoing BCCH pdu for PHY
BCCH_PDU BCCH_pdu;
/// Outgoing BCCH DCI allocation
uint32_t BCCH_alloc_pdu;
/// Outgoing CCCH pdu for PHY
CCCH_PDU CCCH_pdu;
/// Outgoing DLSCH pdu for PHY
@@ -962,6 +966,25 @@ void mac_UE_out_of_sync_ind(u8 Mod_id,u32 frame, u16 CH_index);
// eNB functions
/* \brief This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
@param Mod_id Instance ID of eNB
@param frame Index of frame
@param subframe Index of current subframe
@param dl_pow_off Pointer to store resulting power offset for DCI
@param pre_nb_available_rbs Pointer to store number of remaining rbs after scheduling
@param N_RBS Number of resource block groups
@param rb_alloc_sub Table of resource block groups allocated to each UE
*/
void dlsch_scheduler_pre_processor (unsigned char Mod_id,
u32 frame,
unsigned char subframe,
u8 *dl_pow_off,
u16 *pre_nb_available_rbs,
int N_RBGS,
unsigned char rballoc_sub_UE[NUMBER_OF_UE_MAX][N_RBGS_MAX]);
/* \brief Function to trigger the eNB scheduling procedure. It is called by PHY at the beginning of each subframe, \f$n$\f
and generates all DLSCH allocations for subframe \f$n\f$ and ULSCH allocations for subframe \f$n+k$\f. The resultant DCI_PDU is
ready after returning from this call.
@@ -988,7 +1011,6 @@ DCI_PDU *get_dci_sdu(u8 Mod_id,u32 frame,u8 subframe);
*/
void initiate_ra_proc(u8 Mod_id,u32 frame, u16 preamble_index,s16 timing_offset,u8 sect_id,u8 subframe,u8 f_id);
/* \brief Function in eNB to fill RAR pdu when requested by PHY. This provides a single RAR SDU for the moment and returns the t-CRNTI.
@param Mod_id Instance ID of eNB
@param dlsch_buffer Pointer to DLSCH input buffer

2175
openair2/LAYER2/MAC/eNB_scheduler.c
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File diff suppressed because it is too large Load Diff

3
openair2/LAYER2/MAC/lte_transport_init.c
View File

@@ -17,7 +17,7 @@ void init_transport_channels(unsigned char transmission_mode) {
UL_alloc_pdu.TPC = 0;
UL_alloc_pdu.cqi_req = 1;
/*
BCCH_alloc_pdu.type = 1;
BCCH_alloc_pdu.vrb_type = 0;
BCCH_alloc_pdu.rballoc = BCCH_RB_ALLOC;
@@ -36,6 +36,7 @@ void init_transport_channels(unsigned char transmission_mode) {
BCCH_alloc_pdu_fdd.mcs = 1;
BCCH_alloc_pdu_fdd.harq_pid = 0;
BCCH_alloc_pdu_fdd.TPC = 1; // set to 3 PRB
*/
DLSCH_alloc_pdu1A.type = 1;
DLSCH_alloc_pdu1A.vrb_type = 0;

85
openair2/LAYER2/MAC/main.c
View File

@@ -139,6 +139,7 @@ int mac_top_init(int eMBMS_active, u8 cba_group_active){
unsigned char Mod_id,i,j;
RA_TEMPLATE *RA_template;
UE_TEMPLATE *UE_template;
int size_bytes1,size_bytes2,size_bits1,size_bits2;
LOG_I(MAC,"[MAIN] Init function start:Nb_UE_INST=%d\n",NB_UE_INST);
if (NB_UE_INST>0) {
@@ -209,21 +210,81 @@ int mac_top_init(int eMBMS_active, u8 cba_group_active){
RA_template = (RA_TEMPLATE *)&eNB_mac_inst[i].RA_template[0];
for (j=0;j<NB_RA_PROC_MAX;j++) {
if (mac_xface->lte_frame_parms->frame_type == TDD) {
memcpy((void *)&RA_template[j].RA_alloc_pdu1[0],(void *)&RA_alloc_pdu,sizeof(DCI1A_5MHz_TDD_1_6_t));
memcpy((void *)&RA_template[j].RA_alloc_pdu2[0],(void *)&DLSCH_alloc_pdu1A,sizeof(DCI1A_5MHz_TDD_1_6_t));
RA_template[j].RA_dci_size_bytes1 = sizeof(DCI1A_5MHz_TDD_1_6_t);
RA_template[j].RA_dci_size_bytes2 = sizeof(DCI1A_5MHz_TDD_1_6_t);
RA_template[j].RA_dci_size_bits1 = sizeof_DCI1A_5MHz_TDD_1_6_t;
RA_template[j].RA_dci_size_bits2 = sizeof_DCI1A_5MHz_TDD_1_6_t;
switch (mac_xface->lte_frame_parms->N_RB_DL) {
case 6:
size_bytes1 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
size_bits1 = sizeof_DCI1A_1_5MHz_TDD_1_6_t;
size_bits2 = sizeof_DCI1A_1_5MHz_TDD_1_6_t;
break;
case 25:
size_bytes1 = sizeof(DCI1A_5MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_5MHz_TDD_1_6_t);
size_bits1 = sizeof_DCI1A_5MHz_TDD_1_6_t;
size_bits2 = sizeof_DCI1A_5MHz_TDD_1_6_t;
break;
case 50:
size_bytes1 = sizeof(DCI1A_10MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_10MHz_TDD_1_6_t);
size_bits1 = sizeof_DCI1A_10MHz_TDD_1_6_t;
size_bits2 = sizeof_DCI1A_10MHz_TDD_1_6_t;
break;
case 100:
size_bytes1 = sizeof(DCI1A_20MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_20MHz_TDD_1_6_t);
size_bits1 = sizeof_DCI1A_20MHz_TDD_1_6_t;
size_bits2 = sizeof_DCI1A_20MHz_TDD_1_6_t;
break;
default:
size_bytes1 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
size_bits1 = sizeof_DCI1A_1_5MHz_TDD_1_6_t;
size_bits2 = sizeof_DCI1A_1_5MHz_TDD_1_6_t;
break;
}
}
else {
memcpy((void *)&RA_template[j].RA_alloc_pdu1[0],(void *)&RA_alloc_pdu_fdd,sizeof(DCI1A_5MHz_FDD_t));
memcpy((void *)&RA_template[j].RA_alloc_pdu2[0],(void *)&DLSCH_alloc_pdu1A_fdd,sizeof(DCI1A_5MHz_FDD_t));
RA_template[j].RA_dci_size_bytes1 = sizeof(DCI1A_5MHz_FDD_t);
RA_template[j].RA_dci_size_bytes2 = sizeof(DCI1A_5MHz_FDD_t);
RA_template[j].RA_dci_size_bits1 = sizeof_DCI1A_5MHz_FDD_t;
RA_template[j].RA_dci_size_bits2 = sizeof_DCI1A_5MHz_FDD_t;
switch (mac_xface->lte_frame_parms->N_RB_DL) {
case 6:
size_bytes1 = sizeof(DCI1A_1_5MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_FDD_t);
size_bits1 = sizeof_DCI1A_1_5MHz_FDD_t;
size_bits2 = sizeof_DCI1A_1_5MHz_FDD_t;
break;
case 25:
size_bytes1 = sizeof(DCI1A_5MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_5MHz_FDD_t);
size_bits1 = sizeof_DCI1A_5MHz_FDD_t;
size_bits2 = sizeof_DCI1A_5MHz_FDD_t;
break;
case 50:
size_bytes1 = sizeof(DCI1A_10MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_10MHz_FDD_t);
size_bits1 = sizeof_DCI1A_10MHz_FDD_t;
size_bits2 = sizeof_DCI1A_10MHz_FDD_t;
break;
case 100:
size_bytes1 = sizeof(DCI1A_20MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_20MHz_FDD_t);
size_bits1 = sizeof_DCI1A_20MHz_FDD_t;
size_bits2 = sizeof_DCI1A_20MHz_FDD_t;
break;
default:
size_bytes1 = sizeof(DCI1A_1_5MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_FDD_t);
size_bits1 = sizeof_DCI1A_1_5MHz_FDD_t;
size_bits2 = sizeof_DCI1A_1_5MHz_FDD_t;
break;
}
}
memcpy((void *)&RA_template[j].RA_alloc_pdu1[0],(void *)&RA_alloc_pdu,size_bytes1);
memcpy((void *)&RA_template[j].RA_alloc_pdu2[0],(void *)&DLSCH_alloc_pdu1A,size_bytes2);
RA_template[j].RA_dci_size_bytes1 = size_bytes1;
RA_template[j].RA_dci_size_bytes2 = size_bytes2;
RA_template[j].RA_dci_size_bits1 = size_bits1;
RA_template[j].RA_dci_size_bits2 = size_bits2;
RA_template[j].RA_dci_fmt1 = format1A;
RA_template[j].RA_dci_fmt2 = format1A;
}

164
openair2/LAYER2/MAC/pre_processor.c
View File

@@ -313,26 +313,46 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
unsigned char subframe,
u8 *dl_pow_off,
u16 *pre_nb_available_rbs,
unsigned char rballoc_sub_UE[256][mac_xface->lte_frame_parms->N_RBGS]){
int N_RBGS,
unsigned char rballoc_sub_UE[NUMBER_OF_UE_MAX][N_RBGS_MAX]){
unsigned char next_ue,next_ue1,next_ue2,rballoc_sub[mac_xface->lte_frame_parms->N_RBGS],harq_pid=0,harq_pid1=0,harq_pid2=0,round=0,round1=0,round2=0,total_ue_count=0;
unsigned char MIMO_mode_indicator[mac_xface->lte_frame_parms->N_RBGS];
u16 UE_id,UE_id_sorted[256],granted_UEs,i,ii,j,nb_rbs_required[256],nb_rbs_required_remaining[256],nb_rbs_required_remaining_1[256],i1,i2,i3,r1=0,average_rbs_per_user=0;
u16 UE_id,UE_id_sorted[NUMBER_OF_UE_MAX],granted_UEs,i,ii,j,nb_rbs_required[NUMBER_OF_UE_MAX],nb_rbs_required_remaining[NUMBER_OF_UE_MAX],nb_rbs_required_remaining_1[NUMBER_OF_UE_MAX],i1,i2,i3,r1=0,average_rbs_per_user=0;
u16 rnti,rnti1,rnti2;
LTE_eNB_UE_stats* eNB_UE_stats1;
LTE_eNB_UE_stats* eNB_UE_stats2;
u16 min_rb_unit=2;
u16 min_rb_unit;
switch (mac_xface->lte_frame_parms->N_RB_DL) {
case 6:
min_rb_unit=1;
break;
case 25:
min_rb_unit=2;
break;
case 50:
min_rb_unit=3;
break;
case 100:
min_rb_unit=4;
break;
default:
min_rb_unit=2;
break;
}
granted_UEs = find_dlgranted_UEs(Mod_id);
for(i=0;i<256;i++){
for(i=0;i<NUMBER_OF_UE_MAX;i++){
nb_rbs_required[i] = 0;
UE_id_sorted[i] = i;
dl_pow_off[i] =2;
pre_nb_available_rbs[i] = 0;
nb_rbs_required_remaining[i] = 0;
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++)
for(j=0;j<N_RBGS;j++)
{
MIMO_mode_indicator[j] = 2;
rballoc_sub[j] = 0;
@@ -404,7 +424,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for(j=0;j<N_RBGS;j++){
if((rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue][j] == 0) && (nb_rbs_required_remaining[next_ue]>0)){
@@ -416,15 +436,16 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if(mac_xface->get_transmission_mode(Mod_id,rnti)==5)
dl_pow_off[next_ue] = 1;
// if the total rb is odd
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 1;
if ((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25)||
(mac_xface->lte_frame_parms->N_RB_DL == 50))) {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit+1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit - 1;
}
else {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
else
{
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
}
}
}
@@ -445,7 +466,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for(j=0;j<N_RBGS;j++){
if((rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue][j] == 0) && (nb_rbs_required_remaining[next_ue]>0)){
@@ -457,14 +478,15 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if(mac_xface->get_transmission_mode(Mod_id,rnti)==5)
dl_pow_off[next_ue] = 1;
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 1;
if((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25)||
(mac_xface->lte_frame_parms->N_RB_DL == 50))){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit + 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit - 1;
}
else
{
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 2;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 2;
else {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
}
}
@@ -486,7 +508,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for(j=0;j<N_RBGS;j++){
if((rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue][j] == 0) && (nb_rbs_required_remaining[next_ue]>0)){
@@ -498,15 +520,16 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if(mac_xface->get_transmission_mode(Mod_id,rnti)==5)
dl_pow_off[next_ue] = 1;
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 1;
if((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25)||
(mac_xface->lte_frame_parms->N_RB_DL == 50))){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit + 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit - 1;
}
else {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
else
{
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 2;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 2;
}
}
}
}
@@ -530,9 +553,9 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if ((mac_get_rrc_status(Mod_id,1,next_ue1) >= RRC_RECONFIGURED) && (round1==0) && (mac_xface->get_transmission_mode(Mod_id,rnti1)==5) && (dl_pow_off[next_ue1] != 1)) {
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j+=2){
for(j=0;j<N_RBGS;j+=2){
if((((j == (mac_xface->lte_frame_parms->N_RBGS-1))&& (rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue1][j] == 0)) || ((j < (mac_xface->lte_frame_parms->N_RBGS-1)) && (rballoc_sub[j+1] == 0) && (rballoc_sub_UE[next_ue1][j+1] == 0))) && (nb_rbs_required_remaining[next_ue1]>0)){
if((((j == (N_RBGS-1))&& (rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue1][j] == 0)) || ((j < (N_RBGS-1)) && (rballoc_sub[j+1] == 0) && (rballoc_sub_UE[next_ue1][j+1] == 0))) && (nb_rbs_required_remaining[next_ue1]>0)){
for (ii = i+1;ii < granted_UEs;ii++) {
@@ -546,7 +569,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if ((mac_get_rrc_status(Mod_id,1,next_ue2) >= RRC_RECONFIGURED) && (round2==0) && (mac_xface->get_transmission_mode(Mod_id,rnti2)==5) && (dl_pow_off[next_ue2] != 1)) {
if((((j == (mac_xface->lte_frame_parms->N_RBGS-1)) && (rballoc_sub_UE[next_ue2][j] == 0)) || ((j < (mac_xface->lte_frame_parms->N_RBGS-1)) && (rballoc_sub_UE[next_ue2][j+1] == 0))) && (nb_rbs_required_remaining[next_ue2]>0)){
if((((j == (N_RBGS-1)) && (rballoc_sub_UE[next_ue2][j] == 0)) || ((j < (N_RBGS-1)) && (rballoc_sub_UE[next_ue2][j+1] == 0))) && (nb_rbs_required_remaining[next_ue2]>0)){
if((((eNB_UE_stats2->DL_pmi_single^eNB_UE_stats1->DL_pmi_single)<<(14-j))&0xc000)== 0x4000){ //MU-MIMO only for 25 RBs configuration
@@ -555,7 +578,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
rballoc_sub_UE[next_ue2][j] = 1;
MIMO_mode_indicator[j] = 0;
if (j< mac_xface->lte_frame_parms->N_RBGS-1) {
if (j< N_RBGS-1) {
rballoc_sub[j+1] = 1;
rballoc_sub_UE[next_ue1][j+1] = 1;
rballoc_sub_UE[next_ue2][j+1] = 1;
@@ -568,19 +591,20 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue1] = nb_rbs_required_remaining[next_ue1] - 1;
pre_nb_available_rbs[next_ue1] = pre_nb_available_rbs[next_ue1] + 1;
nb_rbs_required_remaining[next_ue2] = nb_rbs_required_remaining[next_ue2] - 1;
pre_nb_available_rbs[next_ue2] = pre_nb_available_rbs[next_ue2] + 1;
if ((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25) ||
(mac_xface->lte_frame_parms->N_RB_DL == 50))){
nb_rbs_required_remaining[next_ue1] = nb_rbs_required_remaining[next_ue1] - min_rb_unit+1;
pre_nb_available_rbs[next_ue1] = pre_nb_available_rbs[next_ue1] + min_rb_unit-1;
nb_rbs_required_remaining[next_ue2] = nb_rbs_required_remaining[next_ue2] - min_rb_unit+1;
pre_nb_available_rbs[next_ue2] = pre_nb_available_rbs[next_ue2] + min_rb_unit-1;
}
else {
nb_rbs_required_remaining[next_ue1] = nb_rbs_required_remaining[next_ue1] - 4;
pre_nb_available_rbs[next_ue1] = pre_nb_available_rbs[next_ue1] + 4;
nb_rbs_required_remaining[next_ue2] = nb_rbs_required_remaining[next_ue2] - 4;
pre_nb_available_rbs[next_ue2] = pre_nb_available_rbs[next_ue2] + 4;
}
else
{
nb_rbs_required_remaining[next_ue1] = nb_rbs_required_remaining[next_ue1] - 4;
pre_nb_available_rbs[next_ue1] = pre_nb_available_rbs[next_ue1] + 4;
nb_rbs_required_remaining[next_ue2] = nb_rbs_required_remaining[next_ue2] - 4;
pre_nb_available_rbs[next_ue2] = pre_nb_available_rbs[next_ue2] + 4;
}
break;
}
}
@@ -603,7 +627,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
if ((mac_get_rrc_status(Mod_id,1,next_ue) >= RRC_RECONFIGURED) && (round==0)) {
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for(j=0;j<N_RBGS;j++){
if((rballoc_sub[j] == 0) && (rballoc_sub_UE[next_ue][j] == 0) && (nb_rbs_required_remaining[next_ue]>0)){
@@ -618,15 +642,16 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
MIMO_mode_indicator[j] = 1;
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 1;
if((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25)||
(mac_xface->lte_frame_parms->N_RB_DL == 50))){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit+1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] +min_rb_unit-1;
}
else {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
else
{
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 2;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 2;
}
break;
case 5:
@@ -639,15 +664,16 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
MIMO_mode_indicator[j] = 1;
if((j == mac_xface->lte_frame_parms->N_RBGS-1) && (mac_xface->lte_frame_parms->N_RB_DL%2 == 1)){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 1;
if((j == N_RBGS-1) &&
((mac_xface->lte_frame_parms->N_RB_DL == 25)||
(mac_xface->lte_frame_parms->N_RB_DL == 50))){
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit+1;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit-1;
}
else {
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - min_rb_unit;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + min_rb_unit;
}
else
{
nb_rbs_required_remaining[next_ue] = nb_rbs_required_remaining[next_ue] - 2;
pre_nb_available_rbs[next_ue] = pre_nb_available_rbs[next_ue] + 2;
}
}
break;
default:
@@ -662,7 +688,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
i1=0;
i2=0;
i3=0;
for (j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for (j=0;j<N_RBGS;j++){
if(MIMO_mode_indicator[j] == 2)
i1 = i1+1;
else if(MIMO_mode_indicator[j] == 1)
@@ -672,13 +698,13 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
}
if((i1 < mac_xface->lte_frame_parms->N_RBGS) && (i2>0) && (i3==0))
if((i1 < N_RBGS) && (i2>0) && (i3==0))
PHY_vars_eNB_g[Mod_id]->check_for_SUMIMO_transmissions = PHY_vars_eNB_g[Mod_id]->check_for_SUMIMO_transmissions + 1;
if(i3 == mac_xface->lte_frame_parms->N_RBGS && i1==0 && i2==0)
if(i3 == N_RBGS && i1==0 && i2==0)
PHY_vars_eNB_g[Mod_id]->FULL_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id]->FULL_MUMIMO_transmissions + 1;
if((i1 < mac_xface->lte_frame_parms->N_RBGS) && (i3 > 0))
if((i1 < N_RBGS) && (i3 > 0))
PHY_vars_eNB_g[Mod_id]->check_for_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id]->check_for_MUMIMO_transmissions + 1;
PHY_vars_eNB_g[Mod_id]->check_for_total_transmissions = PHY_vars_eNB_g[Mod_id]->check_for_total_transmissions + 1;
@@ -691,7 +717,7 @@ void dlsch_scheduler_pre_processor (unsigned char Mod_id,
LOG_D(PHY,"******************Scheduling Information for UE%d ************************\n",UE_id);
LOG_D(PHY,"dl power offset UE%d = %d \n",UE_id,dl_pow_off[UE_id]);
LOG_D(PHY,"***********RB Alloc for every subband for UE%d ***********\n",UE_id);
for(j=0;j<mac_xface->lte_frame_parms->N_RBGS;j++){
for(j=0;j<N_RBGS;j++){
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[i] = rballoc_sub_UE[UE_id][i];
LOG_D(PHY,"RB Alloc for UE%d and Subband%d = %d\n",UE_id,j,rballoc_sub_UE[UE_id][j]);
}

2
openair2/LAYER2/MAC/ue_procedures.c
View File

@@ -401,7 +401,7 @@ void ue_decode_si(u8 Mod_id,u32 frame, u8 eNB_index, void *pdu,u16 len) {
int i;
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_SI, VCD_FUNCTION_IN);
// LOG_D(MAC,"[UE %d] Frame %d Sending SI to RRC (LCID Id %d)\n",Mod_id,frame,BCCH);
LOG_D(MAC,"[UE %d] Frame %d Sending SI to RRC (LCID Id %d,len %d)\n",Mod_id,frame,BCCH,len);
mac_rrc_data_ind(Mod_id,
frame,

2
openair2/NAS/DRIVER/MESH/Makefile
View File

@@ -28,7 +28,6 @@ IS_KERNEL_SUBVERSION_GREATER_THAN_22=$(shell if [ $(SUBVERSION) -ge 22 ] ; then
IS_KERNEL_SUBVERSION_GREATER_THAN_29=$(shell if [ $(SUBVERSION) -ge 29 ] ; then echo true ; fi)
IS_KERNEL_SUBVERSION_GREATER_THAN_30=$(shell if [ $(SUBVERSION) -ge 30 ] ; then echo true ; fi)
IS_KERNEL_SUBVERSION_GREATER_THAN_32=$(shell if [ $(SUBVERSION) -ge 32 ] ; then echo true ; fi)
# Add global rule for V3 kernels
IS_KERNEL_SUBVERSION_GREATER_THAN_301= "false"
@@ -38,6 +37,7 @@ ifeq ($(KERNEL_MAIN_VERSION),3)
IS_KERNEL_SUBVERSION_GREATER_THAN_30 = "true"
IS_KERNEL_SUBVERSION_GREATER_THAN_32 = "true"
IS_KERNEL_SUBVERSION_GREATER_THAN_301=$(shell if [ $(SUBVERSION) -ge 1 ] ; then echo true ; fi)
IS_KERNEL_SUBVERSION_GREATER_THAN_307=$(shell if [ $(SUBVERSION) -ge 7 ] ; then echo true ; fi)
endif
GT2622 = $(if $(IS_KERNEL_SUBVERSION_GREATER_THAN_22),-DKERNEL_VERSION_GREATER_THAN_2622=1)