mirror of
https://gitlab.eurecom.fr/oai/openairinterface5g.git
synced 2026-07-13 04:30:28 +00:00
fix: exclude sim binary and stats file from git
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> Signed-off-by: Raymond Knopp <raymond.knopp@eurecom.fr>
This commit is contained in:
2
openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder_hexagon/sim/.gitignore
vendored
Normal file
2
openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder_hexagon/sim/.gitignore
vendored
Normal file
@@ -0,0 +1,2 @@
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ldpc_sim_test
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sim_stats.txt
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Binary file not shown.
@@ -1,396 +0,0 @@
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PMU Statistics collection began at pcycle 0 and stopped at pcycle 19734630
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The rev_id used in the simulation is 0x00008c73 (-mv73na_1)
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Arch-lib reports full run simulation cycles:
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All counters:
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QDSP6_clk_cnt : 19734630
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0x01:COUNTER0_OVERFLOW:0
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||||
0x02:COUNTER2_OVERFLOW:0
|
||||
0x03:COMMITTED_PKT_ANY:6578045
|
||||
0x04:COMMITTED_PKT_BSB:0
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||||
0x05:COUNTER4_OVERFLOW:0
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||||
0x06:COUNTER6_OVERFLOW:0
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||||
0x07:COMMITTED_PKT_B2B:0
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||||
0x08:COMMITTED_PKT_SMT:0
|
||||
0x0a:CYCLES_5_THREAD_RUNNING:0
|
||||
0x0b:CYCLES_6_THREAD_RUNNING:0
|
||||
0x0c:COMMITTED_PKT_T0:6578045
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||||
0x0d:COMMITTED_PKT_T1:0
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||||
0x0e:COMMITTED_PKT_T2:0
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||||
0x0f:COMMITTED_PKT_T3:0
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||||
0x10:COMMITTED_PKT_T4:0
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||||
0x11:COMMITTED_PKT_T5:0
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||||
0x12:ICACHE_DEMAND_MISS:0
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||||
0x13:DCACHE_DEMAND_MISS:0
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||||
0x14:DCACHE_STORE_MISS:0
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||||
0x15:COMMITTED_PKT_T6:0
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||||
0x16:COMMITTED_PKT_T7:0
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||||
0x17:CU_PKT_READY_NOT_DISPATCHED:0
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||||
0x18:COMMITTED_PKT_5_THREAD_RUNNING:0
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||||
0x19:COMMITTED_PKT_6_THREAD_RUNNING:0
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||||
0x1a:COMMITTED_PKT_7_THREAD_RUNNING:0
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||||
0x1b:COMMITTED_PKT_8_THREAD_RUNNING:0
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||||
0x1c:IU_L1S_ACCESS:0
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||||
0x1d:IU_L1S_PREFETCH:0
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||||
0x1e:IU_L1S_AXIS_STALL:0
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||||
0x1f:IU_L1S_NO_GRANT:0
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||||
0x20:ANY_IU_REPLAY:0
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0x21:ANY_DU_REPLAY:0
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0x22:CYCLES_7_THREAD_RUNNING:0
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0x23:ISSUED_PACKETS:0
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0x24:LOOPCACHE_PACKETS:0
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0x25:COMMITTED_PKT_1_THREAD_RUNNING:6578044
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0x26:COMMITTED_PKT_2_THREAD_RUNNING:0
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0x27:COMMITTED_PKT_3_THREAD_RUNNING:0
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0x28:THREAD_LMH_THROTTLE:0
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||||
0x29:LMH_THROTTLE:0
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||||
0x2a:COMMITTED_INSTS:0
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||||
0x2b:COMMITTED_TC1_INSTS:0
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||||
0x2c:COMMITTED_PRIVATE_INSTS:0
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||||
0x2d:GLOBAL_POWERLIMITS_OVER:0
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0x2e:CYCLES_8_THREAD_RUNNING:0
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||||
0x2f:COMMITTED_PKT_4_THREAD_RUNNING:0
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||||
0x30:COMMITTED_LOADS:0
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0x31:COMMITTED_STORES:0
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0x32:COMMITTED_MEMOPS:0
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0x33:COMMITTED_NOPS:0
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0x34:ISSUED_INSTS:0
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||||
0x35:DISPATCHED_PACKETS:0
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||||
0x36:DISPATCHED_INSTS:0
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||||
0x37:COMMITTED_PROGRAM_FLOW_INSTS:0
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||||
0x38:COMMITTED_PKT_CHANGED_FLOW:0
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||||
0x39:COMMITTED_PKT_ENDLOOP:0
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||||
0x3a:PST_USED_P0P1BUSY:0
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0x3b:CYCLES_1_THREAD_RUNNING:19734135
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0x3c:CYCLES_2_THREAD_RUNNING:0
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||||
0x3d:CYCLES_3_THREAD_RUNNING:0
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||||
0x3e:CYCLES_4_THREAD_RUNNING:0
|
||||
0x3f:AXI_LINE128_READ_REQUEST:0
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||||
0x40:AXI_READ_REQUEST:0
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||||
0x41:AXI_LINE32_READ_REQUEST:0
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||||
0x42:AXI_WRITE_REQUEST:0
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||||
0x43:AXI_LINE32_WRITE_REQUEST:0
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||||
0x44:AHB_READ_REQUEST:0
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||||
0x45:AHB_WRITE_REQUEST:0
|
||||
0x46:AXI_LINE128_WRITE_REQUEST:0
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||||
0x47:AXI_SLAVE_MULTI_BEAT_ACCESS:0
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||||
0x48:AXI_SLAVE_SINGLE_BEAT_ACCESS:0
|
||||
0x49:AXI2_READ_REQUEST:0
|
||||
0x4a:AXI2_LINE32_READ_REQUEST:0
|
||||
0x4b:AXI2_WRITE_REQUEST:0
|
||||
0x4c:AXI2_LINE32_WRITE_REQUEST:0
|
||||
0x4d:AXI2_CONGESTION:0
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||||
0x50:COMMITTED_FPS:0
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||||
0x51:REDIRECT_BIMODAL_MISPREDICT:0
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||||
0x52:REDIRECT_TARGET_MISPREDICT:0
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||||
0x53:REDIRECT_LOOP_MISPREDICT:0
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||||
0x54:REDIRECT_MISC:0
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||||
0x55:AXI_LINE256_WRITE_REQUEST:0
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||||
0x56:NUM_PACKET_CRACKED:0
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||||
0x58:JTLB_MISS:2
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||||
0x5a:COMMITTED_PKT_RETURN:0
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||||
0x5b:COMMITTED_PKT_INDIRECT_JUMP:0
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||||
0x5c:COMMITTED_BIMODAL_BRANCH_INSTS:0
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||||
0x5f:VTCM_FIFO_FULL_CYCLES:0
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||||
0x60:DU_STORE_BUFFER_COALESCED:0
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||||
0x61:DU_L1S_LOAD_ACCESS:0
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||||
0x62:ICACHE_ACCESS:0
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||||
0x63:BTB_HIT:0
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||||
0x64:BTB_MISS:0
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||||
0x65:IU_DEMAND_SECONDARY_MISS:0
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||||
0x67:FAST_FETCH_KILLED:0
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||||
0x69:FETCHED_PACKETS_DROPPED:0
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||||
0x6b:IU_PREFETCHES_SENT_TO_L2:0
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||||
0x6c:ITLB_MISS:0
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||||
0x72:FETCH_2_CYCLE:0
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||||
0x73:FETCH_3_CYCLE:0
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||||
0x75:L2_IU_SECONDARY_MISS:0
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||||
0x76:L2_IU_ACCESS:0
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||||
0x77:L2_IU_MISS:0
|
||||
0x78:L2_IU_PREFETCH_ACCESS:0
|
||||
0x79:L2_IU_PREFETCH_MISS:0
|
||||
0x7c:L2_DU_READ_ACCESS:0
|
||||
0x7d:L2_DU_READ_MISS:0
|
||||
0x7e:L2FETCH_ACCESS:0
|
||||
0x7f:L2FETCH_MISS:0
|
||||
0x81:L2_ACCESS:0
|
||||
0x82:L2_PIPE_CONFLICT_STALL:0
|
||||
0x83:L2_TAG_ARRAY_CONFLICT:0
|
||||
0x87:TCM_DU_ACCESS:0
|
||||
0x88:TCM_DU_READ_ACCESS:0
|
||||
0x89:TCM_IU_ACCESS:0
|
||||
0x8a:L2_CASTOUT:0
|
||||
0x8b:L2_DU_STORE_ACCESS:0
|
||||
0x8c:L2_DU_STORE_MISS:0
|
||||
0x8d:L2_DU_PREFETCH_ACCESS:0
|
||||
0x8e:L2_DU_PREFETCH_MISS:0
|
||||
0x90:L2_DU_LOAD_SECONDARY_MISS:0
|
||||
0x91:L2FETCH_COMMAND:0
|
||||
0x92:L2FETCH_COMMAND_KILLED:0
|
||||
0x93:L2FETCH_COMMAND_OVERWRITE:0
|
||||
0x94:L2FETCH_ACCESS_CREDIT_FAIL:0
|
||||
0x95:AXI_SLAVE_READ_BUSY:0
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||||
0x96:AXI_SLAVE_WRITE_BUSY:0
|
||||
0x97:L2_ACCESS_EVEN:0
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||||
0x98:CLADE_HIGH_PRIO_L2_ACCESS:0
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||||
0x99:CLADE_LOW_PRIO_L2_ACCESS:0
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0x9a:CLADE_HIGH_PRIO_L2_MISS:0
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||||
0x9b:CLADE_LOW_PRIO_L2_MISS:0
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||||
0x9c:CLADE_HIGH_PRIO_EXCEPTION:0
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||||
0x9d:CLADE_LOW_PRIO_EXCEPTION:0
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||||
0x9e:AXI2_SLAVE_READ_BUSY:0
|
||||
0x9f:AXI2_SLAVE_WRITE_BUSY:0
|
||||
0xa0:ANY_DU_STALL:0
|
||||
0xa1:DU_BANK_CONFLICT_REPLAY:0
|
||||
0xa2:DU_CREDIT_REPLAY:0
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||||
0xa3:L2_FIFO_FULL_REPLAY:0
|
||||
0xa4:DU_STORE_BUFFER_FULL_REPLAY:0
|
||||
0xa7:DU_SNOOP_REQUEST:0
|
||||
0xa8:DU_FILL_REPLAY:0
|
||||
0xa9:PST_3STORETYPE_SBCONF_REPLAY:0
|
||||
0xac:DU_READ_TO_L2:0
|
||||
0xad:DU_WRITE_TO_L2:0
|
||||
0xae:PST_3LDST_L2FIFOCONF_REPLAY:0
|
||||
0xaf:DCZERO_COMMITTED:0
|
||||
0xb0:L2ITCM_IU_READ:0
|
||||
0xb1:L2ITCM_DU_READ:0
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||||
0xb2:L2ITCM_DU_WRITE:0
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||||
0xb3:DTLB_MISS:0
|
||||
0xb4:L2ITCM_BIMODAL_WRITES_SUCCESS:0
|
||||
0xb6:STORE_BUFFER_HIT_REPLAY:0
|
||||
0xb7:STORE_BUFFER_FORCE_REPLAY:0
|
||||
0xb8:TAG_WRITE_CONFLICT_REPLAY:0
|
||||
0xb9:SMT_BANK_CONFLICT:0
|
||||
0xba:PORT_CONFLICT_REPLAY:0
|
||||
0xbb:L2ITCM_BIMODAL_WRITES_DROPPED:0
|
||||
0xbc:L2ITCM_IU_PREFETCH_READ:0
|
||||
0xbd:PAGE_CROSS_REPLAY:0
|
||||
0xbe:PST_STORE_SENTON_OTHPORT:0
|
||||
0xbf:DU_DEMAND_SECONDARY_MISS:0
|
||||
0xc0:DU_MISC_REPLAY:0
|
||||
0xc1:GUARDBUF_SETMATCH_CRACKING_REPLAY:0
|
||||
0xc2:DU_STATE_REPLAY:0
|
||||
0xc3:DCFETCH_COMMITTED:0
|
||||
0xc4:DCFETCH_HIT:0
|
||||
0xc5:DCFETCH_MISS:0
|
||||
0xc6:DCACHE_EVICTION_IN_PIPE_REPLAY:0
|
||||
0xc7:STBUF_MATCH_PARTIAL_CRACK_REPLAY:0
|
||||
0xc8:DU_LOAD_UNCACHEABLE:0
|
||||
0xc9:DU_DUAL_LOAD_UNCACHEABLE:0
|
||||
0xca:DU_STORE_UNCACHEABLE:0
|
||||
0xcb:DU_STORE_RELEASE_CREDIT_STALL:0
|
||||
0xcd:AXI_LINE256_READ_REQUEST:0
|
||||
0xce:AXI_LINE64_READ_REQUEST:0
|
||||
0xcf:AXI_LINE64_WRITE_REQUEST:0
|
||||
0xd1:AHB_8_READ_REQUEST:0
|
||||
0xd3:L2FETCH_COMMAND_PAGE_TERMINATION:0
|
||||
0xd5:L2_DU_STORE_COALESCE:0
|
||||
0xd6:L2_STORE_LINK:0
|
||||
0xd7:L2_SCOREBOARD_70_PERCENT_FULL:0
|
||||
0xd8:L2_SCOREBOARD_80_PERCENT_FULL:0
|
||||
0xd9:L2_SCOREBOARD_90_PERCENT_FULL:0
|
||||
0xda:L2_SCOREBOARD_FULL_REJECT:0
|
||||
0xdc:L2_EVICTION_BUFFERS_FULL:0
|
||||
0xdd:AHB_MULTI_BEAT_READ_REQUEST:0
|
||||
0xdf:L2_DU_LOAD_SECONDARY_MISS_ON_SW_PREFETCH:0
|
||||
0xe0:L2FETCH_DROP:0
|
||||
0xe5:THREAD_OFF_PVIEW_CYCLES:0
|
||||
0xe6:ARCH_LOCK_PVIEW_CYCLES:0
|
||||
0xe7:REDIRECT_PVIEW_CYCLES:0
|
||||
0xe8:IU_NO_PKT_PVIEW_CYCLES:0
|
||||
0xe9:DU_CACHE_MISS_PVIEW_CYCLES:0
|
||||
0xea:DU_BUSY_OTHER_PVIEW_CYCLES:0
|
||||
0xeb:CU_BUSY_PVIEW_CYCLES:0
|
||||
0xec:SMT_DU_CONFLICT_PVIEW_CYCLES:0
|
||||
0xed:COPROC_BUSY_PVIEW_CYCLES:0
|
||||
0xee:DU_UNCACHED_PVIEW_CYCLES:0
|
||||
0xef:SYSTEM_BUSY_PVIEW_CYCLES:0
|
||||
0xf1:AXI_LINE128_READ_REQUEST_EVEN:0
|
||||
0xf2:AXI_READ_REQUEST_EVEN:0
|
||||
0xf3:AXI_LINE32_READ_REQUEST_EVEN:0
|
||||
0xf4:AXI_WRITE_REQUEST_EVEN:0
|
||||
0xf5:AXI_LINE32_WRITE_REQUEST_EVEN:0
|
||||
0xf6:AXI_LINE128_WRITE_REQUEST_EVEN:0
|
||||
0xf8:AXI_LINE64_READ_REQUEST_EVEN:0
|
||||
0xf9:AXI_LINE64_WRITE_REQUEST_EVEN:0
|
||||
0xfa:AXI_WR_CONGESTION_EVEN:0
|
||||
0xfb:AXI_INCOMPLETE_WRITE_REQUEST_EVEN:0
|
||||
0xfc:AXI_LINE256_READ_REQUEST_EVEN:0
|
||||
0xfd:AXI_LINE256_WRITE_REQUEST_EVEN:0
|
||||
0xfe:CYCLES_3_COPROC_THREADS_ONE_CLUSTER:0
|
||||
0x100:HVX_ACTIVE:0
|
||||
0x101:HVX_REG_ORDER:0
|
||||
0x102:HVX_ACC_ORDER:0
|
||||
0x103:HVX_LD_L2_OUTSTANDING:0
|
||||
0x104:HVX_ST_L2_OUTSTANDING:0
|
||||
0x105:HVX_VTCM_OUTSTANDING:0
|
||||
0x106:HVX_SCATGATH_FULL:0
|
||||
0x107:HVX_SCATGATH_IN_FULL:0
|
||||
0x108:HVX_ST_FULL:0
|
||||
0x109:HVX_VOLTAGE_VIRUS_OVER:0
|
||||
0x10a:HVX_VOLTAGE_UNDER:0
|
||||
0x10b:HVX_POWER_OVER:0
|
||||
0x10c:HVX_PKT_PARTIAL:0
|
||||
0x111:HVX_PKT:0
|
||||
0x112:HVX_PKT_THREAD:0
|
||||
0x113:HVX_CORE_VFIFO_FULL_STALL:0
|
||||
0x115:CYCLES_1_HVX_CONTEXTS_RUNNING:0
|
||||
0x116:CYCLES_2_HVX_CONTEXTS_RUNNING:0
|
||||
0x117:CYCLES_3_HVX_CONTEXTS_RUNNING:0
|
||||
0x118:HVXLD_L2:0
|
||||
0x119:HVXLD_L2_TCM:0
|
||||
0x11a:HVXLD_L2_MISS:0
|
||||
0x11b:HVXLD_L2_SECONDARY_MISS:0
|
||||
0x11c:HVXST_L2_WR:0
|
||||
0x11d:HVXST_SLD_CONFLICT:0
|
||||
0x11e:HVXST_VTCM_GATH_CONFLICT:0
|
||||
0x11f:HVXST_L2_CONFLICT:0
|
||||
0x120:HVXST_VTCM_CONFLICT:0
|
||||
0x121:HVXST_L2_FULL:0
|
||||
0x122:HVXST_VTCM_FULL:0
|
||||
0x123:HVXST_L2:0
|
||||
0x124:HVXST_L2_MISS:0
|
||||
0x125:HVXST_L2TCM:0
|
||||
0x126:HVXST_VTCM:0
|
||||
0x127:HVXST_L2_SECODARY_MISS:0
|
||||
0x128:HVXPIPE_ALU:0
|
||||
0x129:HVXPIPE_MPY:0
|
||||
0x12a:HVXPIPE_SHIFT:0
|
||||
0x12b:HVXPIPE_PERM:0
|
||||
0x12c:CYCLES_4_HVX_CONTEXTS_RUNNING:0
|
||||
0x180:COPROC0_PKT_XE:0
|
||||
0x181:COPROC0_FIFO_FULL_STALL:0
|
||||
0x182:COPROC0_VEXTRACT_STALL:0
|
||||
0x183:COPROC0_CYCLES_RUNNING:0
|
||||
0x184:COPROC1_PKT_XE:0
|
||||
0x185:COPROC1_FIFO_FULL_STALL:0
|
||||
0x186:COPROC1_VEXTRACT_STALL:0
|
||||
0x187:COPROC1_CYCLES_RUNNING:0
|
||||
0x188:COPROC2_PKT_XE:0
|
||||
0x189:COPROC2_FIFO_FULL_STALL:0
|
||||
0x18a:COPROC2_VEXTRACT_STALL:0
|
||||
0x18b:COPROC2_CYCLES_RUNNING:0
|
||||
0x18c:COPROC3_PKT_XE:0
|
||||
0x18d:COPROC3_FIFO_FULL_STALL:0
|
||||
0x18e:COPROC3_VEXTRACT_STALL:0
|
||||
0x18f:COPROC3_CYCLES_RUNNING:0
|
||||
0x240:UDMA_ACTIVE_CYCLES:0
|
||||
0x241:UDMA_STALL_DESCRIPTOR_FETCH:0
|
||||
0x243:UDMA_STALL_TLB_MISS:0
|
||||
0x244:UDMA_STALL_MONITOR_GUEST_MODE:0
|
||||
0x245:UDMA_DMPOLL_CYCLES:0
|
||||
0x246:UDMA_DMWAIT_CYCLES:0
|
||||
0x247:UDMA_SYNCHT_CYCLES:0
|
||||
0x248:UDMA_TLBSYNCH_CYCLES:0
|
||||
0x24a:UDMA_DMPOLL:0
|
||||
0x24b:UDMA_DMWAIT:0
|
||||
0x24c:UDMA_TLB_MISS:0
|
||||
0x24d:UDMA_DESCRIPTOR_DONE:0
|
||||
0x24e:UDMA_DMSTART:0
|
||||
0x24f:UDMA_DMLINK:0
|
||||
0x250:UDMA_DMRESUME:0
|
||||
0x251:L2_UDMA_COHERENT_WR:0
|
||||
0x252:L2_UDMA_COHERENT_WR_MISS:0
|
||||
0x253:L2_UDMA_COHERENT_RD:0
|
||||
0x254:L2_UDMA_COHERENT_RD_MISS:0
|
||||
0x255:L2_UDMA_BYPASS_WR:0
|
||||
0x256:L2_UDMA_BYPASS_RD:0
|
||||
0x257:UDMA_VTCM_WR:0
|
||||
0x258:UDMA_VTCM_RD:0
|
||||
0x259:UDMA_DLBC_FETCH:0
|
||||
0x25a:UDMA_DLBC_FETCH_CYCLES:0
|
||||
0x25b:UDMA_UNALIGNED_DESCRIPTOR:0
|
||||
0x25c:UDMA_ORDERING_DESCRIPTOR:0
|
||||
0x25d:UDMA_PADDING_DESCRIPTOR:0
|
||||
0x25e:UDMA_UNALIGNED_RD:0
|
||||
0x25f:UDMA_UNALIGNED_WR:0
|
||||
0x260:UDMA_COHERENT_RD_CYCLES:0
|
||||
0x261:UDMA_COHERENT_WR_CYCLES:0
|
||||
0x262:UDMA_NONCOHERENT_RD_CYCLES:0
|
||||
0x263:UDMA_NONCOHERENT_WR_CYCLES:0
|
||||
0x264:UDMA_VTCM_RD_CYCLES:0
|
||||
0x265:UDMA_VTCM_WR_CYCLES:0
|
||||
0x266:UDMA_RD_BUFFER_LEVEL_LOW:0
|
||||
0x267:UDMA_RD_BUFFER_LEVEL_HALF:0
|
||||
0x268:UDMA_RD_BUFFER_LEVEL_HIGH:0
|
||||
0x269:UDMA_RD_BUFFER_LEVEL_FULL:0
|
||||
0x26c:AXI_SLAVE_VTCM_ACCESS:0
|
||||
0x26d:AXI2_SLAVE_VTCM_ACCESS:0
|
||||
0x26e:AXI_SLAVE_VTCM_RD:0
|
||||
0x26f:AXI2_SLAVE_VTCM_RD:0
|
||||
0x270:L2_UDMA_VTCM_CONGESTION:0
|
||||
0x271:L2_AXIS_VTCM_CONGESTION:0
|
||||
0x272:L2_AXI2_SLAVE_VTCM_CONGESTION:0
|
||||
0x273:L2_MEMCPY_VTCM_CONGESTION:0
|
||||
0x274:AXI_SLAVE_MULTI_BEAT_ACCESS_ILV0:0
|
||||
0x275:AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV0:0
|
||||
0x276:AXI_SLAVE_MULTI_BEAT_ACCESS_ILV1:0
|
||||
0x277:AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV1:0
|
||||
0x278:AXI_SLAVE_MULTI_BEAT_ACCESS_ILV2:0
|
||||
0x279:AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV2:0
|
||||
0x27a:AXI_SLAVE_MULTI_BEAT_ACCESS_ILV3:0
|
||||
0x27b:AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV3:0
|
||||
0x2fa:L2_CLEAN_CASTOUT:0
|
||||
0x2fb:AXI3_READ_REQUEST:0
|
||||
0x2fc:AXI3_LINE32_READ_REQUEST:0
|
||||
0x2fd:AXI3_WRITE_REQUEST:0
|
||||
0x2fe:AXI3_LINE32_WRITE_REQUEST:0
|
||||
0x2ff:AXI3_RD_CONGESTION:0
|
||||
0x300:CYCLES_1_PACKET_COMMITTED:0
|
||||
0x301:CYCLES_2_PACKET_COMMITTED:0
|
||||
0x302:CYCLES_3_PACKET_COMMITTED:0
|
||||
0x303:CYCLES_4_PACKET_COMMITTED:0
|
||||
0x304:SMT_CLUSTER0:0
|
||||
0x305:SMT_CLUSTER1:0
|
||||
0x306:SMT_INTERCLUSTER:0
|
||||
0x307:SMT_CONFLICT_FOR_REG_READ_OR_CU_FWD:0
|
||||
0x308:COMMITTED_PKT_2_THREAD_RUNNING_2T_PLUS_0T:0
|
||||
0x309:COMMITTED_PKT_2_THREAD_RUNNING_1T_PLUS_1T:0
|
||||
0x30a:COMMITTED_PKT_3_THREAD_RUNNING_3T_PLUS_0T:0
|
||||
0x30b:COMMITTED_PKT_3_THREAD_RUNNING_2T_PLUS_1T:0
|
||||
0x30c:COMMITTED_PKT_4_THREAD_RUNNING_4T_PLUS_0T:0
|
||||
0x30d:COMMITTED_PKT_4_THREAD_RUNNING_3T_PLUS_1T:0
|
||||
0x30e:COMMITTED_PKT_4_THREAD_RUNNING_2T_PLUS_2T:0
|
||||
0x30f:COMMITTED_PKT_5_THREAD_RUNNING_4T_PLUS_1T:0
|
||||
0x310:COMMITTED_PKT_5_THREAD_RUNNING_3T_PLUS_2T:0
|
||||
0x311:COMMITTED_PKT_6_THREAD_RUNNING_4T_PLUS_2T:0
|
||||
0x312:COMMITTED_PKT_6_THREAD_RUNNING_3T_PLUS_3T:0
|
||||
0x313:ICACHE_DEMAND_MISS_PREFETCH_MISS:0
|
||||
0x314:SIMPLE_PACKET:0
|
||||
0x315:AXI3_LINE64_WRITE_REQUEST:0
|
||||
0x316:AXI3_LINE64_READ_REQUEST:0
|
||||
0x317:AXI3_WR_CONGESTION:0
|
||||
0x318:AXI3_INCOMPLETE_WRITE_REQUEST:0
|
||||
0x319:ICACHE_DATA_REPLAY:0
|
||||
0x31c:SMT_PKT_PICKED_BUT_NOT_COMMIT_PVIEW_CYCLES:0
|
||||
0x31d:SMT_PKT_IQ_NO_PKT_PVIEW_CYCLES:0
|
||||
0x31e:SMT_PKT_NOT_SIMPLE_PVIEW_CYCLES:0
|
||||
0x31f:SMT_PKT_NOT_READY_PVIEW_CYCLES:0
|
||||
0x320:SMT_PKT_SLOT_CONFLICT_PVIEW_CYCLES:0
|
||||
0x321:SMT_PKT_REG_FWD_BLOCK_PVIEW_CYCLES:0
|
||||
0x322:CLADE2_EB_FULL:0
|
||||
0x323:CLADE2_RD_REQ:0
|
||||
0x324:CLADE2_RDCACHE_MISS:0
|
||||
0x325:CLADE2_WR_REQ:0
|
||||
0x326:CLADE2_WRCACHE_MISS:0
|
||||
0x327:AXI_EWD_REQUEST:0
|
||||
0x328:AXI_EWD_REQUEST_EVEN:0
|
||||
0x329:AXI_CMO_REQUEST:0
|
||||
0x32a:AXI_CMO_REQUEST_EVEN:0
|
||||
0x32b:ICACHE_DEMAND_MISS_PREFETCH_MISS_IU0:0
|
||||
0x32c:ICACHE_DEMAND_MISS_PREFETCH_MISS_IU1:0
|
||||
0x330:VMEM_ST_SMT_DU_PORT_CONFLICT_REPLAY:0
|
||||
0x333:DU_SPF_DTLBPGCROSS:0
|
||||
0x334:DU_SPF_DCACHE_HIT:0
|
||||
0x335:DU_SPF_DCACHE_MISS:0
|
||||
0x336:DU_SPF_L2FIFOFULL_RETRY:0
|
||||
0x337:DU_SPF_L2BUFFULL_RETRY:0
|
||||
0x338:DU_SPF_CONFLICT_RETRY:0
|
||||
0x350:DU_NUM_WAY_PREDICTIONS:0
|
||||
0x351:DU_WAY_PRED_REPLAYS:0
|
||||
0x352:DU_BANKCONFLICTREPLAY_INVALID:0
|
||||
|
||||
|
||||
Command line used to invoke simulator:
|
||||
/opt/Hexagon_SDK/6.4.0.2/tools/HEXAGON_Tools/19.0.04/Tools/bin/hexagon-sim -mv73 --statsfile sim_stats.txt ./ldpc_sim_test
|
||||
Reference in New Issue
Block a user