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split7.2_d
| Author | SHA1 | Date | |
|---|---|---|---|
|
|
b59dadab9d |
@@ -25,7 +25,6 @@
|
||||
<a href="https://hub.docker.com/r/oaisoftwarealliance/oai-nr-ue"><img alt="Docker Pulls" src="https://img.shields.io/docker/pulls/oaisoftwarealliance/oai-nr-ue?label=NR-UE%20docker%20pulls"></a>
|
||||
<a href="https://hub.docker.com/r/oaisoftwarealliance/oai-enb"><img alt="Docker Pulls" src="https://img.shields.io/docker/pulls/oaisoftwarealliance/oai-enb?label=eNB%20docker%20pulls"></a>
|
||||
<a href="https://hub.docker.com/r/oaisoftwarealliance/oai-lte-ue"><img alt="Docker Pulls" src="https://img.shields.io/docker/pulls/oaisoftwarealliance/oai-lte-ue?label=LTE-UE%20docker%20pulls"></a>
|
||||
<a href="https://hub.docker.com/r/oaisoftwarealliance/oai-nr-cuup"><img alt="Docker Pulls" src="https://img.shields.io/docker/pulls/oaisoftwarealliance/oai-nr-cuup?label=NR-CUUP%20docker%20pulls"></a>
|
||||
</p>
|
||||
|
||||
# OpenAirInterface License #
|
||||
|
||||
@@ -30,11 +30,11 @@ global:
|
||||
nrpsbchsim: dedale
|
||||
nrprachsim: dedale
|
||||
nrpucchsim: dedale
|
||||
nrulschsim: demophon
|
||||
nrulsim3gpp: demophon
|
||||
nrulsimmimo: demophon
|
||||
nrulsimmisc: demophon
|
||||
nrulsimscfdma: demophon
|
||||
polartest: demophon
|
||||
smallblocktest: demophon
|
||||
ulsim: demophon
|
||||
nrulschsim: theseus
|
||||
nrulsim3gpp: theseus
|
||||
nrulsimmimo: theseus
|
||||
nrulsimmisc: theseus
|
||||
nrulsimscfdma: theseus
|
||||
polartest: theseus
|
||||
smallblocktest: theseus
|
||||
ulsim: theseus
|
||||
|
||||
@@ -19,7 +19,7 @@ gNBs =
|
||||
|
||||
////////// Physical parameters:
|
||||
|
||||
min_rxtxtime = 5;
|
||||
min_rxtxtime = 2;
|
||||
do_SRS = 0;
|
||||
force_256qam_off = 1;
|
||||
pdsch_AntennaPorts_N1 = 1;
|
||||
|
||||
@@ -21,7 +21,7 @@ In this tutorial we describe how to configure and run a 5G end-to-end setup with
|
||||
|
||||
Minimum hardware requirements:
|
||||
- Laptop/Desktop/Server for OAI CN5G and OAI gNB
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.4-desktop-amd64.iso)
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.3-desktop-amd64.iso)
|
||||
- CPU: 8 cores x86_64 @ 3.5 GHz
|
||||
- RAM: 32 GB
|
||||
- Laptop for UE
|
||||
|
||||
@@ -21,7 +21,7 @@ In this tutorial we describe how to configure and run a 5G end-to-end setup with
|
||||
|
||||
Minimum hardware requirements:
|
||||
- Laptop/Desktop/Server for OAI CN5G and OAI gNB
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.4-desktop-amd64.iso)
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.3-desktop-amd64.iso)
|
||||
- CPU: 8 cores x86_64 @ 3.5 GHz
|
||||
- RAM: 32 GB
|
||||
|
||||
|
||||
@@ -21,11 +21,11 @@ In this tutorial we describe how to configure and run a 5G end-to-end setup with
|
||||
|
||||
Minimum hardware requirements:
|
||||
- Laptop/Desktop/Server for OAI CN5G and OAI gNB
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.4-desktop-amd64.iso)
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.3-desktop-amd64.iso)
|
||||
- CPU: 8 cores x86_64 @ 3.5 GHz
|
||||
- RAM: 32 GB
|
||||
- Laptop for UE
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.4-desktop-amd64.iso)
|
||||
- Operating System: [Ubuntu 22.04 LTS](https://releases.ubuntu.com/22.04/ubuntu-22.04.3-desktop-amd64.iso)
|
||||
- CPU: 8 cores x86_64 @ 3.5 GHz
|
||||
- RAM: 8 GB
|
||||
- [USRP B210](https://www.ettus.com/all-products/ub210-kit/), [USRP N300](https://www.ettus.com/all-products/USRP-N300/) or [USRP X300](https://www.ettus.com/all-products/x300-kit/)
|
||||
|
||||
@@ -114,7 +114,11 @@ database:
|
||||
## general single_nssai configuration
|
||||
## Defines YAML anchors, which are reused in the config file
|
||||
snssais:
|
||||
- &embb_slice
|
||||
- &embb_slice1
|
||||
sst: 1
|
||||
- &embb_slice2
|
||||
sst: 1
|
||||
- &embb_slice3
|
||||
sst: 1
|
||||
|
||||
############## NF-specific configuration
|
||||
@@ -141,7 +145,9 @@ amf:
|
||||
mnc: 01
|
||||
tac: 0x0001
|
||||
nssai:
|
||||
- *embb_slice
|
||||
- *embb_slice1
|
||||
- *embb_slice2
|
||||
- *embb_slice3
|
||||
supported_integrity_algorithms:
|
||||
- "NIA1"
|
||||
- "NIA2"
|
||||
@@ -172,25 +178,29 @@ smf:
|
||||
# follows the SmfInfo datatype from 3GPP TS 29.510
|
||||
smf_info:
|
||||
sNssaiSmfInfoList:
|
||||
- sNssai: *embb_slice
|
||||
- sNssai: *embb_slice1
|
||||
dnnSmfInfoList:
|
||||
- dnn: "oai"
|
||||
- sNssai: *embb_slice2
|
||||
dnnSmfInfoList:
|
||||
- dnn: "openairinterface"
|
||||
- sNssai: *embb_slice3
|
||||
dnnSmfInfoList:
|
||||
- dnn: "ims"
|
||||
local_subscription_infos:
|
||||
- single_nssai: *embb_slice
|
||||
- single_nssai: *embb_slice1
|
||||
dnn: "oai"
|
||||
qos_profile:
|
||||
5qi: 9
|
||||
session_ambr_ul: "10Gbps"
|
||||
session_ambr_dl: "10Gbps"
|
||||
- single_nssai: *embb_slice
|
||||
- single_nssai: *embb_slice2
|
||||
dnn: "openairinterface"
|
||||
qos_profile:
|
||||
5qi: 9
|
||||
session_ambr_ul: "10Gbps"
|
||||
session_ambr_dl: "10Gbps"
|
||||
- single_nssai: *embb_slice
|
||||
- single_nssai: *embb_slice3
|
||||
dnn: "ims"
|
||||
qos_profile:
|
||||
5qi: 9
|
||||
@@ -206,10 +216,14 @@ upf:
|
||||
- host: oai-smf # To be used for PFCP association in case of no-NRF
|
||||
upf_info:
|
||||
sNssaiUpfInfoList:
|
||||
- sNssai: *embb_slice
|
||||
- sNssai: *embb_slice1
|
||||
dnnUpfInfoList:
|
||||
- dnn: "oai"
|
||||
- sNssai: *embb_slice2
|
||||
dnnUpfInfoList:
|
||||
- dnn: "openairinterface"
|
||||
- sNssai: *embb_slice3
|
||||
dnnUpfInfoList:
|
||||
- dnn: "ims"
|
||||
|
||||
## DNN configuration
|
||||
|
||||
@@ -167,11 +167,14 @@ services:
|
||||
public_net:
|
||||
ipv4_address: 192.168.70.135
|
||||
networks:
|
||||
# public_net:
|
||||
# external:
|
||||
# name: demo-oai-public-net
|
||||
public_net:
|
||||
driver: bridge
|
||||
name: oai-cn5g-public-net
|
||||
name: demo-oai-public-net
|
||||
ipam:
|
||||
config:
|
||||
- subnet: 192.168.70.128/26
|
||||
driver_opts:
|
||||
com.docker.network.bridge.name: "oai-cn5g"
|
||||
com.docker.network.bridge.name: "demo-oai"
|
||||
|
||||
100
docker/Dockerfile.base.dpdk.ubuntu22
Normal file
100
docker/Dockerfile.base.dpdk.ubuntu22
Normal file
@@ -0,0 +1,100 @@
|
||||
#/*
|
||||
# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
|
||||
# * contributor license agreements. See the NOTICE file distributed with
|
||||
# * this work for additional information regarding copyright ownership.
|
||||
# * The OpenAirInterface Software Alliance licenses this file to You under
|
||||
# * the OAI Public License, Version 1.1 (the "License"); you may not use this file
|
||||
# * except in compliance with the License.
|
||||
# * You may obtain a copy of the License at
|
||||
# *
|
||||
# * http://www.openairinterface.org/?page_id=698
|
||||
# *
|
||||
# * Unless required by applicable law or agreed to in writing, software
|
||||
# * distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# * See the License for the specific language governing permissions and
|
||||
# * limitations under the License.
|
||||
# *-------------------------------------------------------------------------------
|
||||
# * For more information about the OpenAirInterface (OAI) Software Alliance:
|
||||
# * contact@openairinterface.org
|
||||
# */
|
||||
#---------------------------------------------------------------------
|
||||
#
|
||||
# Dockerfile for the Open-Air-Interface BUILD service
|
||||
# Valid for Ubuntu 20.04
|
||||
#
|
||||
#---------------------------------------------------------------------
|
||||
|
||||
|
||||
FROM ubuntu:jammy AS ran-base
|
||||
ARG NEEDED_GIT_PROXY
|
||||
ENV DEBIAN_FRONTEND=noninteractive
|
||||
ENV TZ=Europe/Paris
|
||||
ENV BUILD_UHD_FROM_SOURCE=True
|
||||
ENV UHD_VERSION=4.4.0.0
|
||||
|
||||
#install developers pkg/repo
|
||||
RUN apt-get update && \
|
||||
DEBIAN_FRONTEND=noninteractive apt-get upgrade --yes && \
|
||||
DEBIAN_FRONTEND=noninteractive apt-get install --yes \
|
||||
#gcc needed for build_oai
|
||||
build-essential \
|
||||
psmisc \
|
||||
git \
|
||||
xxd \
|
||||
# python3-pip for conf template generation
|
||||
python3-pip && \
|
||||
pip3 install --ignore-installed pyyaml
|
||||
|
||||
# Add "Tini - A tiny but valid init for containers", https://github.com/krallin/tini
|
||||
# it will be copied into target containers, to print exit numbers and handle signals properly
|
||||
ENV TINI_VERSION v0.19.0
|
||||
ADD https://github.com/krallin/tini/releases/download/${TINI_VERSION}/tini /tini
|
||||
RUN chmod +x /tini
|
||||
|
||||
# In some network environments, GIT proxy is required
|
||||
RUN /bin/bash -c "if [[ -v NEEDED_GIT_PROXY ]]; then git config --global http.proxy $NEEDED_GIT_PROXY; fi"
|
||||
|
||||
#DPDK
|
||||
WORKDIR /dpdk/
|
||||
RUN apt-get -y install wget xz-utils libnuma-dev meson pkg-config
|
||||
RUN wget http://fast.dpdk.org/rel/dpdk-20.11.9.tar.xz
|
||||
RUN tar xvf dpdk-20.11.9.tar.xz && cd
|
||||
|
||||
WORKDIR /dpdk/dpdk-stable-20.11.9
|
||||
RUN meson build
|
||||
RUN ninja -C build
|
||||
RUN ninja install -C build
|
||||
RUN echo "/usr/local/lib" > /etc/ld.so.conf.d/local-lib.conf
|
||||
RUN echo "/usr/local/lib64" >> /etc/ld.so.conf.d/local-lib.conf
|
||||
RUN ldconfig
|
||||
|
||||
RUN pkg-config --libs libdpdk --static
|
||||
|
||||
WORKDIR /phy/
|
||||
RUN git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git phy/
|
||||
WORKDIR /phy/phy/
|
||||
RUN git checkout oran_e_maintenance_release_v1.0
|
||||
|
||||
COPY cmake_targets/tools/oran_fhi_integration_patches/E/oaioran_E.patch .
|
||||
RUN git apply oaioran_E.patch
|
||||
WORKDIR /phy/phy/fhi_lib/lib
|
||||
RUN RTE_SDK=~/dpdk/dpdk-stable-20.11.9/ XRAN_DIR=/phy/phy/fhi_lib make
|
||||
|
||||
# Copying only the needed files to create ran-base
|
||||
WORKDIR /oai-ran/cmake_targets/tools
|
||||
COPY cmake_targets/tools/build_helper \
|
||||
cmake_targets/tools/uhd-4.x-tdd-patch.diff \
|
||||
./
|
||||
|
||||
WORKDIR /oai-ran/cmake_targets
|
||||
COPY cmake_targets/build_oai .
|
||||
|
||||
WORKDIR /oai-ran
|
||||
COPY oaienv .
|
||||
|
||||
#run build_oai -I to get the builder image
|
||||
RUN /bin/sh oaienv && \
|
||||
cd cmake_targets && \
|
||||
mkdir -p log && \
|
||||
./build_oai -I
|
||||
44
docker/Dockerfile.build.split72.ubuntu22
Normal file
44
docker/Dockerfile.build.split72.ubuntu22
Normal file
@@ -0,0 +1,44 @@
|
||||
#/*
|
||||
# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
|
||||
# * contributor license agreements. See the NOTICE file distributed with
|
||||
# * this work for additional information regarding copyright ownership.
|
||||
# * The OpenAirInterface Software Alliance licenses this file to You under
|
||||
# * the OAI Public License, Version 1.1 (the "License"); you may not use this file
|
||||
# * except in compliance with the License.
|
||||
# * You may obtain a copy of the License at
|
||||
# *
|
||||
# * http://www.openairinterface.org/?page_id=698
|
||||
# *
|
||||
# * Unless required by applicable law or agreed to in writing, software
|
||||
# * distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# * See the License for the specific language governing permissions and
|
||||
# * limitations under the License.
|
||||
# *-------------------------------------------------------------------------------
|
||||
# * For more information about the OpenAirInterface (OAI) Software Alliance:
|
||||
# * contact@openairinterface.org
|
||||
# */
|
||||
#---------------------------------------------------------------------
|
||||
#
|
||||
# Dockerfile for the Open-Air-Interface BUILD service
|
||||
# Valid for Ubuntu 20.04
|
||||
#
|
||||
#---------------------------------------------------------------------
|
||||
|
||||
FROM ran-base:latest as ran-build
|
||||
ARG BUILD_OPTION
|
||||
|
||||
RUN rm -Rf /oai-ran
|
||||
WORKDIR /oai-ran
|
||||
COPY . .
|
||||
|
||||
# build all targets so final targets can be created afterwards
|
||||
RUN /bin/sh oaienv && \
|
||||
cd cmake_targets && \
|
||||
mkdir -p log && \
|
||||
./build_oai -c --ninja \
|
||||
--gNB \
|
||||
-t oran_fhlib_5g \
|
||||
--cmake-opt -Dxran_LOCATION=/phy/phy/fhi_lib/lib $BUILD_OPTION && \
|
||||
# Mainly to see if the sanitize option was perfectly executed
|
||||
ldd ran_build/build/nr-softmodem
|
||||
@@ -526,14 +526,6 @@ void processSlotTX(void *arg)
|
||||
PHY_VARS_NR_UE *UE = rxtxD->UE;
|
||||
nr_phy_data_tx_t phy_data = {0};
|
||||
|
||||
// Force sequential execution, even if we launch in // for all slots
|
||||
// at least ULstatus variable is a pure race condition that is quickly detected by assert() in the code because one thread sets it
|
||||
// to active, so the other thread try to steal&run the ul work
|
||||
if (rxtxD->stream_status == STREAM_STATUS_SYNCED) {
|
||||
notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo + proc->nr_slot_tx);
|
||||
delNotifiedFIFO_elt(res);
|
||||
}
|
||||
|
||||
if (UE->if_inst)
|
||||
UE->if_inst->slot_indication(UE->Mod_id);
|
||||
|
||||
@@ -568,6 +560,11 @@ void processSlotTX(void *arg)
|
||||
instead,
|
||||
we may run in place the processSlotTX() when the conditions are met (when a decreasing tx_wait_for_dlsch[slot] will become 0)
|
||||
It will remove the condition signals (for a thread safe semaphore or counter) and make the system simpler
|
||||
This require also other modifications to
|
||||
remove txFifo that is also a big issue
|
||||
add out of order RF board sending, because,
|
||||
if we encode and send tx slot as soon as we can,
|
||||
it will be thrown out of order, especially in TDD mode
|
||||
*/
|
||||
notifiedFIFO_elt_t *res = pollNotifiedFIFO(UE->tx_resume_ind_fifo + proc->nr_slot_tx);
|
||||
if (res)
|
||||
@@ -593,11 +590,6 @@ void processSlotTX(void *arg)
|
||||
phy_procedures_nrUE_TX(UE, proc, &phy_data);
|
||||
}
|
||||
|
||||
notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(int), 0, NULL, NULL);
|
||||
int *msgData = (int *)NotifiedFifoData(newElt);
|
||||
int newslot = (proc->nr_slot_tx + 1) % UE->frame_parms.slots_per_frame;
|
||||
*msgData = newslot;
|
||||
pushNotifiedFIFO(UE->tx_resume_ind_fifo + newslot, newElt);
|
||||
RU_write(rxtxD);
|
||||
}
|
||||
|
||||
@@ -751,7 +743,7 @@ void *UE_thread(void *arg)
|
||||
PHY_VARS_NR_UE *UE = (PHY_VARS_NR_UE *) arg;
|
||||
// int tx_enabled = 0;
|
||||
void *rxp[NB_ANTENNAS_RX];
|
||||
enum stream_status_e stream_status = STREAM_STATUS_UNSYNC;
|
||||
int start_rx_stream = 0;
|
||||
fapi_nr_config_request_t *cfg = &UE->nrUE_config;
|
||||
int tmp = openair0_device_load(&(UE->rfdevice), &openair0_cfg[0]);
|
||||
AssertFatal(tmp == 0, "Could not load the device\n");
|
||||
@@ -763,6 +755,9 @@ void *UE_thread(void *arg)
|
||||
notifiedFIFO_t nf;
|
||||
initNotifiedFIFO(&nf);
|
||||
|
||||
notifiedFIFO_t txFifo;
|
||||
initNotifiedFIFO(&txFifo);
|
||||
|
||||
notifiedFIFO_t freeBlocks;
|
||||
initNotifiedFIFO_nothreadSafe(&freeBlocks);
|
||||
|
||||
@@ -801,7 +796,7 @@ void *UE_thread(void *arg)
|
||||
intialSyncOffset = syncMsg->rx_offset;
|
||||
}
|
||||
delNotifiedFIFO_elt(res);
|
||||
stream_status = STREAM_STATUS_UNSYNC;
|
||||
start_rx_stream = 0;
|
||||
} else {
|
||||
if (IS_SOFTMODEM_IQPLAYER || IS_SOFTMODEM_IQRECORDER) {
|
||||
// For IQ recorder-player we force synchronization to happen in 280 ms
|
||||
@@ -831,10 +826,9 @@ void *UE_thread(void *arg)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (stream_status == STREAM_STATUS_UNSYNC) {
|
||||
stream_status = STREAM_STATUS_SYNCING;
|
||||
if (start_rx_stream == 0) {
|
||||
start_rx_stream=1;
|
||||
syncInFrame(UE, &sync_timestamp, intialSyncOffset);
|
||||
openair0_write_reorder_clear_context(&UE->rfdevice);
|
||||
shiftForNextFrame = 0; // will be used to track clock drift
|
||||
// read in first symbol
|
||||
AssertFatal(UE->frame_parms.ofdm_symbol_size + UE->frame_parms.nb_prefix_samples0
|
||||
@@ -943,18 +937,25 @@ void *UE_thread(void *arg)
|
||||
|
||||
// Start TX slot processing here. It runs in parallel with RX slot processing
|
||||
// in current code, DURATION_RX_TO_TX constant is the limit to get UL data to encode from a RX slot
|
||||
notifiedFIFO_elt_t *newTx = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_tx, NULL, processSlotTX);
|
||||
notifiedFIFO_elt_t *newTx = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_tx, &txFifo, processSlotTX);
|
||||
nr_rxtx_thread_data_t *curMsgTx = (nr_rxtx_thread_data_t *)NotifiedFifoData(newTx);
|
||||
curMsgTx->proc = curMsg.proc;
|
||||
curMsgTx->writeBlockSize = writeBlockSize;
|
||||
curMsgTx->proc.timestamp_tx = writeTimestamp;
|
||||
curMsgTx->UE = UE;
|
||||
curMsgTx->tx_wait_for_dlsch = tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
|
||||
curMsgTx->stream_status = stream_status;
|
||||
stream_status = STREAM_STATUS_SYNCED;
|
||||
tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
|
||||
pushTpool(&(get_nrUE_params()->Tpool), newTx);
|
||||
}
|
||||
|
||||
// Wait for TX slot processing to finish
|
||||
// Should be removed when bugs, race conditions, will be fixed
|
||||
notifiedFIFO_elt_t *res;
|
||||
res = pullTpool(&txFifo, &(get_nrUE_params()->Tpool));
|
||||
if (res == NULL)
|
||||
LOG_E(PHY, "Tpool has been aborted\n");
|
||||
else
|
||||
delNotifiedFIFO_elt(res);
|
||||
} // while !oai_exit
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -645,7 +645,7 @@ void clean_UE_harq(PHY_VARS_NR_UE *UE)
|
||||
for (int harq_pid = 0; harq_pid < NR_MAX_ULSCH_HARQ_PROCESSES; harq_pid++) {
|
||||
NR_UL_UE_HARQ_t *ul_harq_process = &UE->ul_harq_processes[harq_pid];
|
||||
ul_harq_process->tx_status = NEW_TRANSMISSION_HARQ;
|
||||
ul_harq_process->ULstatus = SCH_IDLE;
|
||||
ul_harq_process->status = SCH_IDLE;
|
||||
ul_harq_process->round = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1389,20 +1389,6 @@ static void inner_rx(PHY_VARS_gNB *gNB,
|
||||
rel15_ul->qam_mod_order);
|
||||
}
|
||||
|
||||
typedef struct puschSymbolProc_s {
|
||||
PHY_VARS_gNB *gNB;
|
||||
NR_DL_FRAME_PARMS *frame_parms;
|
||||
nfapi_nr_pusch_pdu_t *rel15_ul;
|
||||
int ulsch_id;
|
||||
int slot;
|
||||
int startSymbol;
|
||||
int numSymbols;
|
||||
int16_t *llr;
|
||||
int16_t **llr_layers;
|
||||
int16_t *scramblingSequence;
|
||||
uint32_t nvar;
|
||||
} puschSymbolProc_t;
|
||||
|
||||
static void nr_pusch_symbol_processing(void *arg)
|
||||
{
|
||||
puschSymbolProc_t *rdata=(puschSymbolProc_t*)arg;
|
||||
@@ -1452,10 +1438,8 @@ static void nr_pusch_symbol_processing(void *arg)
|
||||
}
|
||||
// unscrambling
|
||||
int16_t *llr16 = (int16_t*)&rdata->llr[pusch_vars->llr_offset[symbol] * rel15_ul->nrOfLayers];
|
||||
int16_t *s = rdata->scramblingSequence + pusch_vars->llr_offset[symbol] * rel15_ul->nrOfLayers;
|
||||
const int end = nb_re_pusch * rel15_ul->qam_mod_order * rel15_ul->nrOfLayers;
|
||||
for (int i = 0; i < end; i++)
|
||||
llr16[i] = llr_ptr[i] * s[i];
|
||||
for (int i = 0; i < (nb_re_pusch * rel15_ul->qam_mod_order * rel15_ul->nrOfLayers); i++)
|
||||
llr16[i] = llr_ptr[i] * rdata->s[i];
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1471,7 +1455,7 @@ int nr_rx_pusch_tp(PHY_VARS_gNB *gNB,
|
||||
|
||||
NR_gNB_PUSCH *pusch_vars = &gNB->pusch_vars[ulsch_id];
|
||||
pusch_vars->dmrs_symbol = INVALID_VALUE;
|
||||
int nbSymb = 0;
|
||||
gNB->nbSymb = 0;
|
||||
uint32_t bwp_start_subcarrier = ((rel15_ul->rb_start + rel15_ul->bwp_start) * NR_NB_SC_PER_RB + frame_parms->first_carrier_offset) % frame_parms->ofdm_symbol_size;
|
||||
LOG_D(PHY,"pusch %d.%d : bwp_start_subcarrier %d, rb_start %d, first_carrier_offset %d\n", frame,slot,bwp_start_subcarrier, rel15_ul->rb_start, frame_parms->first_carrier_offset);
|
||||
LOG_D(PHY,"pusch %d.%d : ul_dmrs_symb_pos %x\n",frame,slot,rel15_ul->ul_dmrs_symb_pos);
|
||||
@@ -1587,9 +1571,9 @@ int nr_rx_pusch_tp(PHY_VARS_gNB *gNB,
|
||||
gNB->ulsch[ulsch_id].unav_res = unav_res;
|
||||
|
||||
// initialize scrambling sequence //
|
||||
int16_t scramblingSequence[G + 96] __attribute__((aligned(32)));
|
||||
int16_t s[G+96] __attribute__((aligned(32)));
|
||||
|
||||
nr_codeword_unscrambling_init(scramblingSequence, G, 0, rel15_ul->data_scrambling_id, rel15_ul->rnti);
|
||||
nr_codeword_unscrambling_init(s, G, 0, rel15_ul->data_scrambling_id, rel15_ul->rnti);
|
||||
|
||||
// first the computation of channel levels
|
||||
|
||||
@@ -1690,23 +1674,23 @@ int nr_rx_pusch_tp(PHY_VARS_gNB *gNB,
|
||||
rdata->ulsch_id = ulsch_id;
|
||||
rdata->llr = pusch_vars->llr;
|
||||
rdata->llr_layers = pusch_vars->llr_layers;
|
||||
rdata->scramblingSequence = scramblingSequence;
|
||||
rdata->s = &s[pusch_vars->llr_offset[symbol]*rel15_ul->nrOfLayers];
|
||||
rdata->nvar = nvar;
|
||||
|
||||
if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) {
|
||||
nr_pusch_symbol_processing(rdata);
|
||||
} else {
|
||||
pushTpool(&gNB->threadPool, req);
|
||||
nbSymb++;
|
||||
gNB->nbSymb++;
|
||||
}
|
||||
|
||||
LOG_D(PHY, "%d.%d Added symbol %d (count %d) to process, in pipe\n", frame, slot, symbol, nbSymb);
|
||||
LOG_D(PHY,"%d.%d Added symbol %d (count %d) to process, in pipe\n",frame,slot,symbol,gNB->nbSymb);
|
||||
}
|
||||
} // symbol loop
|
||||
|
||||
while (nbSymb) {
|
||||
while (gNB->nbSymb > 0) {
|
||||
notifiedFIFO_elt_t *req = pullTpool(&gNB->respPuschSymb, &gNB->threadPool);
|
||||
nbSymb--;
|
||||
gNB->nbSymb--;
|
||||
delNotifiedFIFO_elt(req);
|
||||
}
|
||||
|
||||
|
||||
@@ -508,10 +508,12 @@ int nr_rx_pbch(PHY_VARS_NR_UE *ue,
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t payload = 0;
|
||||
result->xtra_byte = (out>>24)&0xff;
|
||||
|
||||
const uint64_t payload = reverse_bits(out, NR_POLAR_PBCH_PAYLOAD_BITS);
|
||||
|
||||
for (int i=0; i<NR_POLAR_PBCH_PAYLOAD_BITS; i++)
|
||||
payload |= ((out>>i)&1)<<(NR_POLAR_PBCH_PAYLOAD_BITS-i-1);
|
||||
|
||||
for (int i=0; i<3; i++)
|
||||
result->decoded_output[i] = (uint8_t)((payload>>((3-i)<<3))&0xff);
|
||||
|
||||
|
||||
@@ -47,7 +47,7 @@ typedef struct {
|
||||
/// HARQ tx status
|
||||
harq_result_t tx_status;
|
||||
/// Status Flag indicating for this ULSCH (idle,active,disabled)
|
||||
SCH_status_t ULstatus;
|
||||
SCH_status_t status;
|
||||
/// Last TPC command
|
||||
uint8_t TPC;
|
||||
/// Length of ACK information (bits)
|
||||
|
||||
@@ -557,7 +557,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
|
||||
|
||||
NR_UL_UE_HARQ_t *harq_process_ulsch = NULL;
|
||||
harq_process_ulsch = &UE->ul_harq_processes[harq_pid];
|
||||
harq_process_ulsch->ULstatus = SCH_IDLE;
|
||||
harq_process_ulsch->status = SCH_IDLE;
|
||||
///////////
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
}
|
||||
|
||||
@@ -716,6 +716,7 @@ typedef struct PHY_VARS_gNB_s {
|
||||
notifiedFIFO_t L1_rx_out;
|
||||
notifiedFIFO_t resp_RU_tx;
|
||||
tpool_t threadPool;
|
||||
int nbSymb;
|
||||
int num_pusch_symbols_per_thread;
|
||||
pthread_t L1_rx_thread;
|
||||
int L1_rx_thread_core;
|
||||
@@ -727,6 +728,20 @@ typedef struct PHY_VARS_gNB_s {
|
||||
rt_L1_profiling_t rt_L1_profiling;
|
||||
} PHY_VARS_gNB;
|
||||
|
||||
typedef struct puschSymbolProc_s {
|
||||
PHY_VARS_gNB *gNB;
|
||||
NR_DL_FRAME_PARMS *frame_parms;
|
||||
nfapi_nr_pusch_pdu_t *rel15_ul;
|
||||
int ulsch_id;
|
||||
int slot;
|
||||
int startSymbol;
|
||||
int numSymbols;
|
||||
int16_t *llr;
|
||||
int16_t **llr_layers;
|
||||
int16_t *s;
|
||||
uint32_t nvar;
|
||||
} puschSymbolProc_t;
|
||||
|
||||
struct puschSymbolReqId {
|
||||
uint16_t ulsch_id;
|
||||
uint16_t frame;
|
||||
|
||||
@@ -632,8 +632,6 @@ typedef struct nr_phy_data_s {
|
||||
sl_nr_rx_config_type_enum_t sl_rx_action;
|
||||
|
||||
} nr_phy_data_t;
|
||||
|
||||
enum stream_status_e { STREAM_STATUS_UNSYNC, STREAM_STATUS_SYNCING, STREAM_STATUS_SYNCED};
|
||||
/* this structure is used to pass both UE phy vars and
|
||||
* proc to the function UE_thread_rxn_txnp4
|
||||
*/
|
||||
@@ -644,7 +642,6 @@ typedef struct nr_rxtx_thread_data_s {
|
||||
nr_phy_data_t phy_data;
|
||||
int tx_wait_for_dlsch;
|
||||
int rx_offset;
|
||||
enum stream_status_e stream_status;
|
||||
} nr_rxtx_thread_data_t;
|
||||
|
||||
typedef struct LDPCDecode_ue_s {
|
||||
|
||||
@@ -272,7 +272,7 @@
|
||||
/* - between reception of pdsch and tarnsmission of its acknowlegment */
|
||||
/* - between reception of un uplink grant and its related transmission */
|
||||
// should be 2 as per NR standard, but current UE is not able to perform this value
|
||||
#define NR_UE_CAPABILITY_SLOT_RX_TO_TX (3)
|
||||
#define NR_UE_CAPABILITY_SLOT_RX_TO_TX (2)
|
||||
|
||||
#define DURATION_RX_TO_TX (NR_UE_CAPABILITY_SLOT_RX_TO_TX)
|
||||
|
||||
|
||||
@@ -473,7 +473,7 @@ static void nr_ue_scheduled_response_ul(PHY_VARS_NR_UE *phy, fapi_nr_ul_config_r
|
||||
pdu->pusch_config_pdu.tx_request_body.pdu_length);
|
||||
}
|
||||
|
||||
harq_process_ul_ue->ULstatus = ACTIVE;
|
||||
harq_process_ul_ue->status = ACTIVE;
|
||||
pdu->pdu_type = FAPI_NR_UL_CONFIG_TYPE_DONE; // not handle it any more
|
||||
} break;
|
||||
|
||||
|
||||
@@ -294,7 +294,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, n
|
||||
start_meas(&ue->phy_proc_tx);
|
||||
|
||||
for (uint8_t harq_pid = 0; harq_pid < NR_MAX_ULSCH_HARQ_PROCESSES; harq_pid++) {
|
||||
if (ue->ul_harq_processes[harq_pid].ULstatus == ACTIVE) {
|
||||
if (ue->ul_harq_processes[harq_pid].status == ACTIVE) {
|
||||
nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, gNB_id, phy_data, (c16_t **)&txdataF);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -158,7 +158,7 @@ int CU_handle_F1_SETUP_REQUEST(instance_t instance, sctp_assoc_t assoc_id, uint3
|
||||
if (servedCellInformation->fiveGS_TAC) {
|
||||
req->cell[i].info.tac = malloc(sizeof(*req->cell[i].info.tac));
|
||||
AssertFatal(req->cell[i].info.tac != NULL, "out of memory\n");
|
||||
OCTET_STRING_TO_INT24(servedCellInformation->fiveGS_TAC, *req->cell[i].info.tac);
|
||||
OCTET_STRING_TO_INT16(servedCellInformation->fiveGS_TAC, *req->cell[i].info.tac);
|
||||
LOG_D(F1AP, "req->tac[%d] %d \n", i, *req->cell[i].info.tac);
|
||||
}
|
||||
|
||||
@@ -636,7 +636,7 @@ int CU_handle_gNB_DU_CONFIGURATION_UPDATE(instance_t instance, sctp_assoc_t asso
|
||||
if (servedCellInformation->fiveGS_TAC) {
|
||||
req->cell_to_modify[i].info.tac = malloc(sizeof(*req->cell_to_modify[i].info.tac));
|
||||
AssertFatal(req->cell_to_modify[i].info.tac != NULL, "out of memory\n");
|
||||
OCTET_STRING_TO_INT24(servedCellInformation->fiveGS_TAC, *req->cell_to_modify[i].info.tac);
|
||||
OCTET_STRING_TO_INT16(servedCellInformation->fiveGS_TAC, *req->cell_to_modify[i].info.tac);
|
||||
LOG_D(F1AP, "req->tac[%d] %d \n", i, *req->cell_to_modify[i].info.tac);
|
||||
}
|
||||
|
||||
|
||||
@@ -186,13 +186,12 @@ void prepare_scc(NR_ServingCellConfigCommon_t *scc) {
|
||||
scc->n_TimingAdvanceOffset = CALLOC(1, sizeof(long));
|
||||
scc->ssb_PositionsInBurst = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__ssb_PositionsInBurst));
|
||||
scc->ssb_periodicityServingCell = CALLOC(1,sizeof(long));
|
||||
// scc->rateMatchPatternToAddModList = CALLOC(1,sizeof(struct
|
||||
// NR_ServingCellConfigCommon__rateMatchPatternToAddModList)); scc->rateMatchPatternToReleaseList =
|
||||
// CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToReleaseList));
|
||||
// scc->rateMatchPatternToAddModList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToAddModList));
|
||||
// scc->rateMatchPatternToReleaseList = CALLOC(1,sizeof(struct NR_ServingCellConfigCommon__rateMatchPatternToReleaseList));
|
||||
scc->ssbSubcarrierSpacing = CALLOC(1,sizeof(NR_SubcarrierSpacing_t));
|
||||
scc->tdd_UL_DL_ConfigurationCommon = CALLOC(1,sizeof(struct NR_TDD_UL_DL_ConfigCommon));
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2 = CALLOC(1,sizeof(struct NR_TDD_UL_DL_Pattern));
|
||||
|
||||
|
||||
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB = CALLOC(1,sizeof(NR_ARFCN_ValueNR_t));
|
||||
|
||||
dl_frequencyBandList = CALLOC(1,sizeof(NR_FreqBandIndicatorNR_t));
|
||||
@@ -379,39 +378,6 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
|
||||
*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing=-1;
|
||||
}
|
||||
|
||||
static void fix_tdd_pattern(NR_ServingCellConfigCommon_t *scc)
|
||||
{
|
||||
int pattern_ext = scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity - 7;
|
||||
/* The pattern1 extension is not configured so free the ext1 and dl_UL_TransmissionPeriodicity_v1530
|
||||
* as these shall not be encoded with default values in SIB1
|
||||
*/
|
||||
if (pattern_ext > 0) {
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 = CALLOC(1, sizeof(struct NR_TDD_UL_DL_Pattern__ext1));
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 = CALLOC(1, sizeof(long));
|
||||
*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 = pattern_ext - 1 ;
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity = 5;
|
||||
}
|
||||
|
||||
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2 != NULL) {
|
||||
/* The pattern2 is not configured free the memory these shall not be encoded with default values in SIB1 */
|
||||
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity > 320) {
|
||||
free(scc->tdd_UL_DL_ConfigurationCommon->pattern2);
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2 = NULL;
|
||||
}
|
||||
} else {
|
||||
/* The pattern2 extension is not configured so free the ext1 and dl_UL_TransmissionPeriodicity_v1530
|
||||
* as these shall not be encoded with default values in SIB1
|
||||
*/
|
||||
pattern_ext = scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity - 7;
|
||||
if (pattern_ext > 0) {
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 = CALLOC(1, sizeof(struct NR_TDD_UL_DL_Pattern__ext1));
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530 = CALLOC(1, sizeof(long));
|
||||
*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530 = pattern_ext - 1;
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity = 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) {
|
||||
|
||||
@@ -486,7 +452,11 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) {
|
||||
ASN_STRUCT_FREE(asn_DEF_NR_TDD_UL_DL_ConfigCommon, scc->tdd_UL_DL_ConfigurationCommon);
|
||||
scc->tdd_UL_DL_ConfigurationCommon = NULL;
|
||||
} else { // TDD
|
||||
fix_tdd_pattern(scc);
|
||||
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity > 320 ) {
|
||||
free(scc->tdd_UL_DL_ConfigurationCommon->pattern2);
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern2 = NULL;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if ((int)*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing == -1) {
|
||||
@@ -2045,7 +2015,6 @@ int RCconfig_NR_X2(MessageDef *msg_p, uint32_t i) {
|
||||
memset((void*)scc,0,sizeof(NR_ServingCellConfigCommon_t));
|
||||
prepare_scc(scc);
|
||||
paramdef_t SCCsParams[] = SCCPARAMS_DESC(scc);
|
||||
|
||||
paramlist_def_t SCCsParamList = {GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON, NULL, 0};
|
||||
|
||||
AssertFatal(i < GNBSParams[GNB_ACTIVE_GNBS_IDX].numelt,
|
||||
|
||||
@@ -2072,15 +2072,13 @@ void release_PUCCH_SRS(NR_UE_MAC_INST_t *mac)
|
||||
for (int bwp = 0; bwp < mac->ul_BWPs.count; bwp++) {
|
||||
// release SchedulingRequestResourceConfig instances configured in PUCCH-Config
|
||||
NR_PUCCH_Config_t *pucch_Config = mac->ul_BWPs.array[bwp]->pucch_Config;
|
||||
if (pucch_Config)
|
||||
for (int j = pucch_Config->schedulingRequestResourceToAddModList->list.count; j > 0 ; j--)
|
||||
asn_sequence_del(&pucch_Config->schedulingRequestResourceToAddModList->list, j - 1, 1);
|
||||
for (int j = pucch_Config->schedulingRequestResourceToAddModList->list.count; j > 0 ; j--)
|
||||
asn_sequence_del(&pucch_Config->schedulingRequestResourceToAddModList->list, j - 1, 1);
|
||||
// release SRS-Resource instances configured in SRS-Config
|
||||
// TODO not clear if only SRS-Resources or also the ResourceSet should be released
|
||||
NR_SRS_Config_t *srs_Config = mac->ul_BWPs.array[bwp]->srs_Config;
|
||||
if (srs_Config)
|
||||
for (int j = srs_Config->srs_ResourceToAddModList->list.count; j > 0 ; j--)
|
||||
asn_sequence_del(&srs_Config->srs_ResourceToAddModList->list, j - 1, 1);
|
||||
for (int j = srs_Config->srs_ResourceToAddModList->list.count; j > 0 ; j--)
|
||||
asn_sequence_del(&srs_Config->srs_ResourceToAddModList->list, j - 1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -45,7 +45,7 @@ int16_t get_prach_tx_power(NR_UE_MAC_INST_t *mac)
|
||||
{
|
||||
RA_config_t *ra = &mac->ra;
|
||||
int16_t pathloss = compute_nr_SSB_PL(mac, mac->ssb_measurements.ssb_rsrp_dBm);
|
||||
int16_t ra_preamble_rx_power = (int16_t)(ra->prach_resources.ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss);
|
||||
int16_t ra_preamble_rx_power = (int16_t)(ra->prach_resources.ra_PREAMBLE_RECEIVED_TARGET_POWER - pathloss + 30);
|
||||
return min(ra->prach_resources.RA_PCMAX, ra_preamble_rx_power);
|
||||
}
|
||||
|
||||
|
||||
@@ -58,9 +58,6 @@
|
||||
#include "common/utils/LOG/log.h"
|
||||
#include "common/utils/LOG/vcd_signal_dumper.h"
|
||||
|
||||
#define DEFAULT_P0_NOMINAL_PUCCH_0_DBM 0
|
||||
#define DEFAULT_DELTA_F_PUCCH_0_DB 0
|
||||
|
||||
// #define DEBUG_MIB
|
||||
// #define ENABLE_MAC_PAYLOAD_DEBUG 1
|
||||
// #define DEBUG_RAR
|
||||
@@ -788,10 +785,6 @@ static int nr_ue_process_dci_dl_10(NR_UE_MAC_INST_t *mac,
|
||||
}
|
||||
|
||||
if (dci_ind->rnti != mac->ra.ra_rnti && dci_ind->rnti != SI_RNTI)
|
||||
AssertFatal(1 + dci->pdsch_to_harq_feedback_timing_indicator.val > DURATION_RX_TO_TX,
|
||||
"PDSCH to HARQ feedback time (%d) needs to be higher than DURATION_RX_TO_TX (%d).\n",
|
||||
1 + dci->pdsch_to_harq_feedback_timing_indicator.val,
|
||||
DURATION_RX_TO_TX);
|
||||
|
||||
// set the harq status at MAC for feedback
|
||||
set_harq_status(mac,
|
||||
@@ -1119,12 +1112,6 @@ static int nr_ue_process_dci_dl_11(NR_UE_MAC_INST_t *mac,
|
||||
// according to TS 38.213 Table 9.2.3-1
|
||||
uint8_t feedback_ti = pucch_Config->dl_DataToUL_ACK->list.array[dci->pdsch_to_harq_feedback_timing_indicator.val][0];
|
||||
|
||||
AssertFatal(feedback_ti > DURATION_RX_TO_TX,
|
||||
"PDSCH to HARQ feedback time (%d) needs to be higher than DURATION_RX_TO_TX (%d). Min feedback time set in config "
|
||||
"file (min_rxtxtime).\n",
|
||||
feedback_ti,
|
||||
DURATION_RX_TO_TX);
|
||||
|
||||
// set the harq status at MAC for feedback
|
||||
set_harq_status(mac,
|
||||
dci->pucch_resource_indicator,
|
||||
@@ -1615,7 +1602,6 @@ int nr_ue_configure_pucch(NR_UE_MAC_INST_t *mac,
|
||||
return 0;
|
||||
}
|
||||
|
||||
// PUCCH Power control according to 38.213 section 7.2.1
|
||||
int16_t get_pucch_tx_power_ue(NR_UE_MAC_INST_t *mac,
|
||||
int scs,
|
||||
NR_PUCCH_Config_t *pucch_Config,
|
||||
@@ -1629,16 +1615,10 @@ int16_t get_pucch_tx_power_ue(NR_UE_MAC_INST_t *mac,
|
||||
int O_uci)
|
||||
{
|
||||
NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
|
||||
AssertFatal(current_UL_BWP && current_UL_BWP->pucch_ConfigCommon,
|
||||
"Missing configuration: need UL_BWP and pucch_ConfigCommon to calculate PUCCH tx power\n");
|
||||
int PUCCH_POWER_DEFAULT = 0;
|
||||
// p0_nominal is optional
|
||||
int16_t P_O_NOMINAL_PUCCH = DEFAULT_P0_NOMINAL_PUCCH_0_DBM;
|
||||
if (current_UL_BWP->pucch_ConfigCommon->p0_nominal != NULL) {
|
||||
P_O_NOMINAL_PUCCH = *current_UL_BWP->pucch_ConfigCommon->p0_nominal;
|
||||
}
|
||||
int16_t P_O_NOMINAL_PUCCH = *current_UL_BWP->pucch_ConfigCommon->p0_nominal;
|
||||
|
||||
struct NR_PUCCH_PowerControl *power_config = pucch_Config ? pucch_Config->pucch_PowerControl : NULL;
|
||||
struct NR_PUCCH_PowerControl *power_config = pucch_Config->pucch_PowerControl;
|
||||
|
||||
if (!power_config)
|
||||
return (PUCCH_POWER_DEFAULT);
|
||||
@@ -1663,8 +1643,7 @@ int16_t get_pucch_tx_power_ue(NR_UE_MAC_INST_t *mac,
|
||||
|
||||
int P_O_PUCCH = P_O_NOMINAL_PUCCH + P_O_UE_PUCCH;
|
||||
|
||||
int16_t delta_F_PUCCH = DEFAULT_DELTA_F_PUCCH_0_DB;
|
||||
long *delta_F_PUCCH_config = NULL;
|
||||
int16_t delta_F_PUCCH;
|
||||
int DELTA_TF;
|
||||
uint16_t N_ref_PUCCH;
|
||||
int N_sc_ctrl_RB = 0;
|
||||
@@ -1674,27 +1653,27 @@ int16_t get_pucch_tx_power_ue(NR_UE_MAC_INST_t *mac,
|
||||
case 0:
|
||||
N_ref_PUCCH = 2;
|
||||
DELTA_TF = 10 * log10(N_ref_PUCCH/N_symb_PUCCH);
|
||||
delta_F_PUCCH_config = power_config->deltaF_PUCCH_f0;
|
||||
delta_F_PUCCH = *power_config->deltaF_PUCCH_f0;
|
||||
break;
|
||||
case 1:
|
||||
N_ref_PUCCH = 14;
|
||||
DELTA_TF = 10 * log10(N_ref_PUCCH/N_symb_PUCCH);
|
||||
delta_F_PUCCH_config = power_config->deltaF_PUCCH_f1;
|
||||
delta_F_PUCCH = *power_config->deltaF_PUCCH_f1;
|
||||
break;
|
||||
case 2:
|
||||
N_sc_ctrl_RB = 10;
|
||||
DELTA_TF = get_deltatf(nb_of_prbs, N_symb_PUCCH, freq_hop_flag, add_dmrs_flag, N_sc_ctrl_RB, O_uci);
|
||||
delta_F_PUCCH_config = power_config->deltaF_PUCCH_f2;
|
||||
delta_F_PUCCH = *power_config->deltaF_PUCCH_f2;
|
||||
break;
|
||||
case 3:
|
||||
N_sc_ctrl_RB = 14;
|
||||
DELTA_TF = get_deltatf(nb_of_prbs, N_symb_PUCCH, freq_hop_flag, add_dmrs_flag, N_sc_ctrl_RB, O_uci);
|
||||
delta_F_PUCCH_config = power_config->deltaF_PUCCH_f3;
|
||||
delta_F_PUCCH = *power_config->deltaF_PUCCH_f3;
|
||||
break;
|
||||
case 4:
|
||||
N_sc_ctrl_RB = 14/(nb_pucch_format_4_in_subframes[subframe_number]);
|
||||
DELTA_TF = get_deltatf(nb_of_prbs, N_symb_PUCCH, freq_hop_flag, add_dmrs_flag, N_sc_ctrl_RB, O_uci);
|
||||
delta_F_PUCCH_config = power_config->deltaF_PUCCH_f4;
|
||||
delta_F_PUCCH = *power_config->deltaF_PUCCH_f4;
|
||||
break;
|
||||
default:
|
||||
{
|
||||
@@ -1702,9 +1681,6 @@ int16_t get_pucch_tx_power_ue(NR_UE_MAC_INST_t *mac,
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
if (delta_F_PUCCH_config != NULL) {
|
||||
delta_F_PUCCH = *delta_F_PUCCH_config;
|
||||
}
|
||||
|
||||
if (power_config->twoPUCCH_PC_AdjustmentStates && *power_config->twoPUCCH_PC_AdjustmentStates > 1) {
|
||||
LOG_E(MAC,"PUCCH power control adjustment states with 2 states not yet implemented\n");
|
||||
@@ -1862,17 +1838,10 @@ void order_resources(PUCCH_sched_t *pucch, int num_res)
|
||||
}
|
||||
}
|
||||
|
||||
bool check_overlapping_resources(PUCCH_sched_t *pucch, int j, int o)
|
||||
bool check_overlapping_resources(int curr_start, int curr_length, int next_start, int next_length)
|
||||
{
|
||||
// assuming overlapping means if two resources overlaps in time,
|
||||
// ie share a symbol in the slot regardless of PRB
|
||||
NR_PUCCH_Resource_t *pucch_resource = pucch[j - o].pucch_resource;
|
||||
int curr_start, curr_length;
|
||||
get_pucch_start_symbol_length(pucch_resource, &curr_start, &curr_length);
|
||||
pucch_resource = pucch[j + 1].pucch_resource;
|
||||
int next_start, next_length;
|
||||
get_pucch_start_symbol_length(pucch_resource, &next_start, &next_length);
|
||||
|
||||
if (curr_start == next_start)
|
||||
return true;
|
||||
if (curr_start + curr_length - 1 < next_start)
|
||||
@@ -2218,9 +2187,18 @@ void multiplex_pucch_resource(NR_UE_MAC_INST_t *mac, PUCCH_sched_t *pucch, int n
|
||||
int j = 0;
|
||||
int o = 0;
|
||||
while (j <= num_res - 1) {
|
||||
if ((j < num_res - 1) && check_overlapping_resources(pucch, j, o)) {
|
||||
o++;
|
||||
j++;
|
||||
if (j < num_res - 1) {
|
||||
NR_PUCCH_Resource_t *pucch_resource = pucch[j - o].pucch_resource;
|
||||
int curr_start, curr_length;
|
||||
get_pucch_start_symbol_length(pucch_resource, &curr_start, &curr_length);
|
||||
pucch_resource = pucch[j + 1].pucch_resource;
|
||||
int next_start, next_length;
|
||||
get_pucch_start_symbol_length(pucch_resource, &next_start, &next_length);
|
||||
bool overlap = check_overlapping_resources(curr_start, curr_length, next_start, next_length);
|
||||
if (overlap) {
|
||||
o++;
|
||||
j++;
|
||||
}
|
||||
} else {
|
||||
if (o > 0) {
|
||||
merge_resources(&pucch[j - o], o + 1, pucch_Config);
|
||||
|
||||
@@ -56,11 +56,6 @@
|
||||
#include "LAYER2/RLC/rlc.h"
|
||||
|
||||
//#define SRS_DEBUG
|
||||
#define verifyMutex(a) \
|
||||
{ \
|
||||
int ret = a; \
|
||||
AssertFatal(ret == 0, "Failure in mutex management ret=%d\n", a); \
|
||||
}
|
||||
|
||||
static void nr_ue_prach_scheduler(NR_UE_MAC_INST_t *mac, frame_t frameP, sub_frame_t slotP);
|
||||
static void schedule_ta_command(fapi_nr_dl_config_request_t *dl_config, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment);
|
||||
@@ -70,9 +65,9 @@ void clear_ul_config_request(NR_UE_MAC_INST_t *mac, int scs)
|
||||
int slots = nr_slots_per_frame[scs];
|
||||
for (int i = 0; i < slots ; i++) {
|
||||
fapi_nr_ul_config_request_t *ul_config = mac->ul_config_request + i;
|
||||
verifyMutex(pthread_mutex_lock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_lock(&ul_config->mutex_ul_config);
|
||||
ul_config->number_pdus = 0;
|
||||
verifyMutex(pthread_mutex_unlock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_unlock(&ul_config->mutex_ul_config);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -86,7 +81,7 @@ fapi_nr_ul_config_request_pdu_t *lockGet_ul_config(NR_UE_MAC_INST_t *mac, frame_
|
||||
AssertFatal(mac->ul_config_request != NULL, "mac->ul_config_request not initialized, logic bug\n");
|
||||
fapi_nr_ul_config_request_t *ul_config = mac->ul_config_request + slot_tx;
|
||||
|
||||
verifyMutex(pthread_mutex_lock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_lock(&ul_config->mutex_ul_config);
|
||||
if (ul_config->number_pdus != 0 && (ul_config->frame != frame_tx || ul_config->slot != slot_tx)) {
|
||||
LOG_E(NR_MAC, "Error in ul config consistency, clearing slot %d\n", slot_tx);
|
||||
ul_config->number_pdus = 0;
|
||||
@@ -95,11 +90,12 @@ fapi_nr_ul_config_request_pdu_t *lockGet_ul_config(NR_UE_MAC_INST_t *mac, frame_
|
||||
ul_config->slot = slot_tx;
|
||||
if (ul_config->number_pdus >= FAPI_NR_UL_CONFIG_LIST_NUM) {
|
||||
LOG_E(NR_MAC, "Error in ul config for slot %d, no memory\n", slot_tx);
|
||||
verifyMutex(pthread_mutex_unlock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_unlock(&ul_config->mutex_ul_config);
|
||||
return NULL;
|
||||
}
|
||||
fapi_nr_ul_config_request_pdu_t *pdu = ul_config->ul_config_list + ul_config->number_pdus++;
|
||||
pdu->pdu_type = pdu_type;
|
||||
AssertFatal(!pdu->lock, "no lock in fapi_nr_ul_config_request_pdu_t, aborting");
|
||||
pdu->lock = &ul_config->mutex_ul_config;
|
||||
pdu->privateNBpdus = &ul_config->number_pdus;
|
||||
LOG_D(NR_MAC, "Added ul pdu for %d.%d, type %d\n", frame_tx, slot_tx, pdu_type);
|
||||
@@ -185,28 +181,30 @@ void remove_ul_config_last_item(fapi_nr_ul_config_request_pdu_t *pdu)
|
||||
|
||||
void release_ul_config(fapi_nr_ul_config_request_pdu_t *configPerSlot, bool clearIt)
|
||||
{
|
||||
pthread_mutex_t *lock = configPerSlot->lock;
|
||||
configPerSlot->lock = NULL;
|
||||
if (clearIt)
|
||||
*configPerSlot->privateNBpdus = 0;
|
||||
verifyMutex(pthread_mutex_unlock(configPerSlot->lock));
|
||||
pthread_mutex_unlock(lock);
|
||||
}
|
||||
|
||||
fapi_nr_ul_config_request_pdu_t *fapiLockIterator(fapi_nr_ul_config_request_t *ul_config, frame_t frame_tx, int slot_tx)
|
||||
{
|
||||
verifyMutex(pthread_mutex_lock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_lock(&ul_config->mutex_ul_config);
|
||||
if (ul_config->number_pdus >= FAPI_NR_UL_CONFIG_LIST_NUM) {
|
||||
LOG_E(NR_MAC, "Error in ul config in slot %d no memory\n", ul_config->slot);
|
||||
verifyMutex(pthread_mutex_unlock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_unlock(&ul_config->mutex_ul_config);
|
||||
return NULL;
|
||||
}
|
||||
if (ul_config->number_pdus != 0 && (ul_config->frame != frame_tx || ul_config->slot != slot_tx)) {
|
||||
LOG_E(NR_MAC, "Error in ul config consistency, clearing it slot %d\n", slot_tx);
|
||||
ul_config->number_pdus = 0;
|
||||
verifyMutex(pthread_mutex_unlock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_unlock(&ul_config->mutex_ul_config);
|
||||
return NULL;
|
||||
}
|
||||
if (ul_config->number_pdus >= FAPI_NR_UL_CONFIG_LIST_NUM) {
|
||||
LOG_E(NR_MAC, "Error in ul config for slot %d, no memory\n", slot_tx);
|
||||
verifyMutex(pthread_mutex_unlock(&ul_config->mutex_ul_config));
|
||||
pthread_mutex_unlock(&ul_config->mutex_ul_config);
|
||||
return NULL;
|
||||
}
|
||||
fapi_nr_ul_config_request_pdu_t *pdu = ul_config->ul_config_list + ul_config->number_pdus;
|
||||
@@ -1009,9 +1007,6 @@ void nr_ue_aperiodic_srs_scheduling(NR_UE_MAC_INST_t *mac, long resource_trigger
|
||||
return;
|
||||
}
|
||||
|
||||
AssertFatal(slot_offset > DURATION_RX_TO_TX,
|
||||
"Slot offset between DCI and aperiodic SRS (%d) needs to be higher than DURATION_RX_TO_TX (%d)\n",
|
||||
slot_offset, DURATION_RX_TO_TX);
|
||||
int n_slots_frame = nr_slots_per_frame[current_UL_BWP->scs];
|
||||
int sched_slot = (slot + slot_offset) % n_slots_frame;
|
||||
NR_TDD_UL_DL_ConfigCommon_t *tdd_config = mac->tdd_UL_DL_ConfigurationCommon;
|
||||
@@ -1470,13 +1465,6 @@ int nr_ue_pusch_scheduler(const NR_UE_MAC_INST_t *mac,
|
||||
AssertFatal(1 == 0, "Invalid numerology %i\n", mu);
|
||||
}
|
||||
|
||||
AssertFatal((k2 + delta) > DURATION_RX_TO_TX,
|
||||
"Slot offset (%ld) for Msg3 needs to be higher than DURATION_RX_TO_TX (%d). Please set min_rxtxtime at least to %d in gNB config file or gNBs.[0].min_rxtxtime=%d via command line.\n",
|
||||
k2,
|
||||
DURATION_RX_TO_TX,
|
||||
DURATION_RX_TO_TX,
|
||||
DURATION_RX_TO_TX);
|
||||
|
||||
*slot_tx = (current_slot + k2 + delta) % nr_slots_per_frame[mu];
|
||||
if (current_slot + k2 + delta >= nr_slots_per_frame[mu]){
|
||||
*frame_tx = (current_frame + 1) % 1024;
|
||||
@@ -1485,14 +1473,6 @@ int nr_ue_pusch_scheduler(const NR_UE_MAC_INST_t *mac,
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
AssertFatal(k2 > DURATION_RX_TO_TX,
|
||||
"Slot offset K2 (%ld) needs to be higher than DURATION_RX_TO_TX (%d). Please set min_rxtxtime at least to %d in gNB config file or gNBs.[0].min_rxtxtime=%d via command line.\n",
|
||||
k2,
|
||||
DURATION_RX_TO_TX,
|
||||
DURATION_RX_TO_TX,
|
||||
DURATION_RX_TO_TX);
|
||||
|
||||
if (k2 < 0) { // This can happen when a false DCI is received
|
||||
LOG_W(PHY, "%d.%d. Received k2 %ld\n", current_frame, current_slot, k2);
|
||||
return -1;
|
||||
@@ -1904,12 +1884,13 @@ static void map_ssb_to_ro(NR_UE_MAC_INST_t *mac)
|
||||
|
||||
// Returns a RACH occasion if any matches the SSB idx, the frame and the slot
|
||||
static int get_nr_prach_info_from_ssb_index(prach_association_pattern_t *prach_assoc_pattern,
|
||||
int ssb_idx,
|
||||
uint8_t ssb_idx,
|
||||
int frame,
|
||||
int slot,
|
||||
ssb_list_info_t *ssb_list,
|
||||
prach_occasion_info_t **prach_occasion_info_pp)
|
||||
{
|
||||
ssb_info_t *ssb_info_p;
|
||||
prach_occasion_slot_t *prach_occasion_slot_p = NULL;
|
||||
|
||||
*prach_occasion_info_pp = NULL;
|
||||
@@ -1919,20 +1900,14 @@ static int get_nr_prach_info_from_ssb_index(prach_association_pattern_t *prach_a
|
||||
// - ssb_idx mapped to one of the ROs in that RO slot
|
||||
// - exact slot number
|
||||
// - frame offset
|
||||
int idx_list = ssb_list->nb_ssb_per_index[ssb_idx];
|
||||
ssb_info_t *ssb_info_p = &ssb_list->tx_ssb[idx_list];
|
||||
ssb_info_p = &ssb_list->tx_ssb[ssb_idx];
|
||||
LOG_D(NR_MAC, "checking for prach : ssb_info_p->nb_mapped_ro %d\n", ssb_info_p->nb_mapped_ro);
|
||||
for (int n_mapped_ro = 0; n_mapped_ro < ssb_info_p->nb_mapped_ro; n_mapped_ro++) {
|
||||
LOG_D(NR_MAC,
|
||||
"%d.%d: mapped_ro[%d]->frame.slot %d.%d, prach_assoc_pattern->nb_of_frame %d\n",
|
||||
frame,
|
||||
slot,
|
||||
n_mapped_ro,
|
||||
ssb_info_p->mapped_ro[n_mapped_ro]->frame,
|
||||
ssb_info_p->mapped_ro[n_mapped_ro]->slot,
|
||||
prach_assoc_pattern->nb_of_frame);
|
||||
for (uint8_t n_mapped_ro=0; n_mapped_ro<ssb_info_p->nb_mapped_ro; n_mapped_ro++) {
|
||||
LOG_D(NR_MAC,"%d.%d: mapped_ro[%d]->frame.slot %d.%d, prach_assoc_pattern->nb_of_frame %d\n",
|
||||
frame,slot,n_mapped_ro,ssb_info_p->mapped_ro[n_mapped_ro]->frame,ssb_info_p->mapped_ro[n_mapped_ro]->slot,prach_assoc_pattern->nb_of_frame);
|
||||
if ((slot == ssb_info_p->mapped_ro[n_mapped_ro]->slot) &&
|
||||
(ssb_info_p->mapped_ro[n_mapped_ro]->frame == (frame % prach_assoc_pattern->nb_of_frame))) {
|
||||
|
||||
uint8_t prach_config_period_nb = ssb_info_p->mapped_ro[n_mapped_ro]->frame / prach_assoc_pattern->prach_conf_period_list[0].nb_of_frame;
|
||||
uint8_t frame_nb_in_prach_config_period = ssb_info_p->mapped_ro[n_mapped_ro]->frame % prach_assoc_pattern->prach_conf_period_list[0].nb_of_frame;
|
||||
prach_occasion_slot_p = &prach_assoc_pattern->prach_conf_period_list[prach_config_period_nb].prach_occasion_slot_map[frame_nb_in_prach_config_period][slot];
|
||||
|
||||
@@ -332,186 +332,6 @@ void process_CellGroup(NR_CellGroupConfig_t *CellGroup, NR_UE_info_t *UE)
|
||||
}
|
||||
process_rlcBearerConfig(CellGroup->rlc_BearerToAddModList, CellGroup->rlc_BearerToReleaseList, &UE->UE_sched_ctrl);
|
||||
}
|
||||
static int8_t set_tdd_bmap_period(NR_TDD_UL_DL_Pattern_t pattern, tdd_bitmap_t *tdd_bmap, int8_t curr_total_slot)
|
||||
{
|
||||
int8_t n_dl_slot, n_ul_slot, n_dl_symbols, n_ul_symbols, total_slot = 0;
|
||||
|
||||
n_dl_slot = pattern.nrofDownlinkSlots;
|
||||
n_ul_slot = pattern.nrofUplinkSlots;
|
||||
n_dl_symbols = pattern.nrofDownlinkSymbols;
|
||||
n_ul_symbols = pattern.nrofUplinkSymbols;
|
||||
|
||||
LOG_I(NR_MAC,
|
||||
"Setting TDD configuration period sum of both patterns dl_slot %d ul_slot%d dl_sym %d ul_sym %d\n",
|
||||
n_dl_slot,
|
||||
n_ul_slot,
|
||||
n_dl_symbols,
|
||||
n_ul_symbols);
|
||||
|
||||
total_slot = !(n_ul_symbols + n_dl_symbols) ? n_dl_slot + n_ul_slot : n_dl_slot + n_ul_slot + 1;
|
||||
|
||||
for (int i = 0; i < total_slot; i++) {
|
||||
if (i < n_dl_slot)
|
||||
tdd_bmap[i + curr_total_slot].slot_type = TDD_NR_DOWNLINK_SLOT;
|
||||
else if ((i == n_dl_slot) && (n_ul_symbols + n_dl_symbols)) {
|
||||
tdd_bmap[i + curr_total_slot].slot_type = TDD_NR_MIXED_SLOT;
|
||||
tdd_bmap[i + curr_total_slot].num_dl_symbols = n_dl_symbols;
|
||||
tdd_bmap[i + curr_total_slot].num_ul_symbols = n_ul_symbols;
|
||||
} else if (n_ul_slot)
|
||||
tdd_bmap[i + curr_total_slot].slot_type = TDD_NR_UPLINK_SLOT;
|
||||
}
|
||||
|
||||
LOG_I(NR_MAC, "Setting TDD configuration total slot %d and curr_slot %d\n", total_slot, curr_total_slot);
|
||||
|
||||
return total_slot;
|
||||
}
|
||||
static int get_tdd_period(NR_TDD_UL_DL_ConfigCommon_t *tdd, nfapi_nr_config_request_scf_t *cfg, tdd_bitmap_t *tdd_bmap)
|
||||
{
|
||||
int num_of_patterns = 1;
|
||||
float tdd_ms_period_pattern[] = {0.5, 0.625, 1.0, 1.25, 2.0, 2.5, 5.0, 10.0, 20.0};
|
||||
float tdd_ms_period_ext[] = {3.0, 4.0};
|
||||
float pattern1_ms = 0.0, pattern2_ms = 0.0;
|
||||
int8_t total_slot_pattern1 = 0;
|
||||
NR_TDD_UL_DL_Pattern_t pattern = tdd->pattern1;
|
||||
|
||||
if (pattern.ext1 == NULL) {
|
||||
LOG_D(NR_MAC, "Setting TDD configuration period to dl_UL_TransmissionPeriodicity %ld\n", pattern.dl_UL_TransmissionPeriodicity);
|
||||
pattern1_ms = tdd_ms_period_pattern[pattern.dl_UL_TransmissionPeriodicity];
|
||||
} else {
|
||||
AssertFatal(pattern.ext1->dl_UL_TransmissionPeriodicity_v1530 != NULL,
|
||||
"In %s: scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 is null\n",
|
||||
__FUNCTION__);
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration period to dl_UL_TransmissionPeriodicity_v1530 %ld\n",
|
||||
*pattern.ext1->dl_UL_TransmissionPeriodicity_v1530);
|
||||
pattern1_ms = tdd_ms_period_ext[*pattern.ext1->dl_UL_TransmissionPeriodicity_v1530];
|
||||
}
|
||||
|
||||
total_slot_pattern1 = set_tdd_bmap_period(pattern, tdd_bmap, 0);
|
||||
|
||||
if (tdd->pattern2) {
|
||||
num_of_patterns++;
|
||||
pattern = *tdd->pattern2;
|
||||
if (pattern.ext1 == NULL) {
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD Pattern2 configuration period to dl_UL_TransmissionPeriodicity %ld\n",
|
||||
pattern.dl_UL_TransmissionPeriodicity);
|
||||
pattern2_ms = tdd_ms_period_pattern[pattern.dl_UL_TransmissionPeriodicity];
|
||||
|
||||
} else {
|
||||
AssertFatal(pattern.ext1->dl_UL_TransmissionPeriodicity_v1530 != NULL,
|
||||
"In %s: scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 is null\n",
|
||||
__FUNCTION__);
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD Pattern2 configuration period to dl_UL_TransmissionPeriodicity_v1530 %p\n",
|
||||
pattern.ext1->dl_UL_TransmissionPeriodicity_v1530);
|
||||
pattern2_ms = tdd_ms_period_ext[*pattern.ext1->dl_UL_TransmissionPeriodicity_v1530];
|
||||
}
|
||||
set_tdd_bmap_period((pattern), tdd_bmap, total_slot_pattern1);
|
||||
}
|
||||
bool found_match = false;
|
||||
for (int i = 0; i <= 8; i++) {
|
||||
if ((pattern1_ms + pattern2_ms) == tdd_ms_period_pattern[i]) {
|
||||
LOG_I(NR_MAC,
|
||||
"Setting TDD configuration period value in cfg->tdd_table.tdd_period based on the sum of dl_UL_TransmissionPeriodicity "
|
||||
"from Pattern1 (%f ms) and Pattern2 (%f ms): Total = %f ms\n",
|
||||
pattern1_ms,
|
||||
pattern2_ms,
|
||||
pattern1_ms + pattern2_ms);
|
||||
cfg->tdd_table.tdd_period.value = i;
|
||||
found_match = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
// Assert if no match was found
|
||||
AssertFatal(found_match, "The sum of pattern1_ms and pattern2_ms does not match any value in tdd_ms_period_pattern");
|
||||
|
||||
LOG_I(NR_MAC, "Setting TDD configuration period sum of both patterns %d\n", cfg->tdd_table.tdd_period.value);
|
||||
return num_of_patterns;
|
||||
}
|
||||
|
||||
static int set_multi_tdd_config_nr(nfapi_nr_config_request_scf_t *cfg, int mu, tdd_bitmap_t *tdd_bmap)
|
||||
{
|
||||
int slot_number = 0;
|
||||
int nb_slots_to_set = TDD_CONFIG_NB_FRAMES * (1 << mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME;
|
||||
int nb_periods_per_frame = get_nb_periods_per_frame(cfg->tdd_table.tdd_period.value);
|
||||
int slot_index = 0;
|
||||
|
||||
int nb_slots_per_period = ((1 << mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME) / nb_periods_per_frame;
|
||||
|
||||
cfg->tdd_table.max_tdd_periodicity_list =
|
||||
(nfapi_nr_max_tdd_periodicity_t *)malloc(nb_slots_to_set * sizeof(nfapi_nr_max_tdd_periodicity_t));
|
||||
|
||||
for (int memory_alloc = 0; memory_alloc < nb_slots_to_set; memory_alloc++)
|
||||
cfg->tdd_table.max_tdd_periodicity_list[memory_alloc].max_num_of_symbol_per_slot_list =
|
||||
(nfapi_nr_max_num_of_symbol_per_slot_t *)malloc(NR_NUMBER_OF_SYMBOLS_PER_SLOT
|
||||
* sizeof(nfapi_nr_max_num_of_symbol_per_slot_t));
|
||||
|
||||
while (slot_number != nb_slots_to_set) {
|
||||
slot_index = slot_number % nb_slots_per_period;
|
||||
if (tdd_bmap[slot_index].slot_type == TDD_NR_DOWNLINK_SLOT) {
|
||||
for (int number_of_symbol = 0; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) {
|
||||
cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value = 0;
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration slot_number %d is DL_Slot %d slot_index %d DL_symbol \n",
|
||||
slot_number,
|
||||
slot_index,
|
||||
number_of_symbol);
|
||||
}
|
||||
LOG_I(NR_MAC, "Setting TDD configuration slot_number %d is DL_Slot %d slot_index \n", slot_number, slot_index);
|
||||
slot_number++;
|
||||
}
|
||||
|
||||
if (tdd_bmap[slot_index].slot_type == TDD_NR_MIXED_SLOT) {
|
||||
for (int number_of_symbol = 0; number_of_symbol < tdd_bmap[slot_index].num_dl_symbols; number_of_symbol++) {
|
||||
cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value = 0;
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration slot_number %d is Mixed Slot %d slot_index %d dl_symbol \n",
|
||||
slot_number,
|
||||
slot_index,
|
||||
number_of_symbol);
|
||||
}
|
||||
|
||||
for (int number_of_symbol = tdd_bmap[slot_index].num_dl_symbols;
|
||||
number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT - tdd_bmap[slot_index].num_ul_symbols;
|
||||
number_of_symbol++) {
|
||||
cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value = 2;
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration slot_number %d is Mixed Slot %d slot_index %d gap_symbol \n",
|
||||
slot_number,
|
||||
slot_index,
|
||||
number_of_symbol);
|
||||
}
|
||||
|
||||
for (int number_of_symbol = NR_NUMBER_OF_SYMBOLS_PER_SLOT - tdd_bmap[slot_index].num_ul_symbols;
|
||||
number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT;
|
||||
number_of_symbol++) {
|
||||
cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value = 1;
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration slot_number %d is Mixed Slot %d slot_index %d ul_symbol \n",
|
||||
slot_number,
|
||||
slot_index,
|
||||
number_of_symbol);
|
||||
}
|
||||
LOG_D(NR_MAC, "Setting TDD configuration slot_number %d is MIXED %d slot_index \n", slot_number, slot_index);
|
||||
slot_number++;
|
||||
}
|
||||
|
||||
if (tdd_bmap[slot_index].slot_type == TDD_NR_UPLINK_SLOT) {
|
||||
for (int number_of_symbol = 0; number_of_symbol < NR_NUMBER_OF_SYMBOLS_PER_SLOT; number_of_symbol++) {
|
||||
cfg->tdd_table.max_tdd_periodicity_list[slot_number].max_num_of_symbol_per_slot_list[number_of_symbol].slot_config.value = 1;
|
||||
LOG_D(NR_MAC,
|
||||
"Setting TDD configuration slot_number %d is UL Slot %d slot_index %d ul_symbol \n",
|
||||
slot_number,
|
||||
slot_index,
|
||||
number_of_symbol);
|
||||
}
|
||||
LOG_D(NR_MAC, "Setting TDD configuration slot_number %d is UL_Slot %d slot_index \n", slot_number, slot_index);
|
||||
slot_number++;
|
||||
}
|
||||
}
|
||||
return (nb_periods_per_frame);
|
||||
}
|
||||
|
||||
static void config_common(gNB_MAC_INST *nrmac, nr_pdsch_AntennaPorts_t pdsch_AntennaPorts, int pusch_AntennaPorts, NR_ServingCellConfigCommon_t *scc)
|
||||
{
|
||||
@@ -807,16 +627,23 @@ static void config_common(gNB_MAC_INST *nrmac, nr_pdsch_AntennaPorts_t pdsch_Ant
|
||||
if (cfg->cell_config.frame_duplex_type.value == TDD) {
|
||||
cfg->tdd_table.tdd_period.tl.tag = NFAPI_NR_CONFIG_TDD_PERIOD_TAG;
|
||||
cfg->num_tlv++;
|
||||
|
||||
int num_tdd_patterns = get_tdd_period(scc->tdd_UL_DL_ConfigurationCommon, cfg, nrmac->tdd_slot_bitmap);
|
||||
int periods_per_frame = 0;
|
||||
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 == NULL) {
|
||||
cfg->tdd_table.tdd_period.value = scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity;
|
||||
} else {
|
||||
AssertFatal(scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 != NULL,
|
||||
"In %s: scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530 is null\n",
|
||||
__FUNCTION__);
|
||||
cfg->tdd_table.tdd_period.value = *scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
|
||||
}
|
||||
LOG_I(NR_MAC, "Setting TDD configuration period to %d\n", cfg->tdd_table.tdd_period.value);
|
||||
int periods_per_frame = set_tdd_config_nr(cfg,
|
||||
frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing,
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots,
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols,
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots,
|
||||
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols);
|
||||
|
||||
LOG_I(NR_MAC, "Setting TDD configuration period to %d num_tdd_patterns %d\n", cfg->tdd_table.tdd_period.value, num_tdd_patterns);
|
||||
|
||||
periods_per_frame = set_multi_tdd_config_nr(cfg,
|
||||
frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing,
|
||||
nrmac->tdd_slot_bitmap);
|
||||
|
||||
AssertFatal(periods_per_frame > 0, "TDD configuration cannot be configured\n");
|
||||
if (frequency_range == FR2) {
|
||||
LOG_I(NR_MAC, "Configuring TDD beam association to default\n");
|
||||
nrmac->tdd_beam_association = malloc16(periods_per_frame * sizeof(int16_t));
|
||||
@@ -920,9 +747,6 @@ void nr_mac_configure_sib1(gNB_MAC_INST *nrmac, const f1ap_plmn_t *plmn, uint64_
|
||||
NR_BCCH_DL_SCH_Message_t *sib1 = get_SIB1_NR(scc, plmn, cellID, tac);
|
||||
cc->sib1 = sib1;
|
||||
cc->sib1_bcch_length = encode_SIB1_NR(sib1, cc->sib1_bcch_pdu, sizeof(cc->sib1_bcch_pdu));
|
||||
LOG_E(NR_MAC, "----------------- ASN1 ENCODER PRINT START ----------------- \n");
|
||||
xer_fprint(stdout, &asn_DEF_NR_BCCH_DL_SCH_Message, sib1);
|
||||
LOG_E(NR_MAC, "----------------- ASN1 ENCODER PRINT END----------------- \n");
|
||||
AssertFatal(cc->sib1_bcch_length > 0, "could not encode SIB1\n");
|
||||
}
|
||||
|
||||
|
||||
@@ -722,13 +722,6 @@ typedef struct f1_config_t {
|
||||
uint32_t gnb_id; // associated gNB's ID, not used in DU itself
|
||||
} f1_config_t;
|
||||
|
||||
enum slot_type { TDD_NR_DOWNLINK_SLOT, TDD_NR_UPLINK_SLOT, TDD_NR_MIXED_SLOT };
|
||||
typedef struct tdd_bitmap {
|
||||
enum slot_type slot_type;
|
||||
uint8_t num_dl_symbols;
|
||||
uint8_t num_ul_symbols;
|
||||
} tdd_bitmap_t;
|
||||
|
||||
/*! \brief top level eNB MAC structure */
|
||||
typedef struct gNB_MAC_INST_s {
|
||||
/// Ethernet parameters for northbound midhaul interface
|
||||
@@ -818,7 +811,6 @@ typedef struct gNB_MAC_INST_s {
|
||||
uint64_t dlsch_slot_bitmap[3];
|
||||
/// bitmap of ULSCH slots, can hold up to 160 slots
|
||||
uint64_t ulsch_slot_bitmap[3];
|
||||
tdd_bitmap_t tdd_slot_bitmap[64];
|
||||
|
||||
/// maximum number of slots before a UE will be scheduled ULSCH automatically
|
||||
uint32_t ulsch_max_frame_inactivity;
|
||||
|
||||
@@ -941,7 +941,7 @@ uint8_t do_NR_DLInformationTransfer(uint8_t *buffer,
|
||||
ASN_STRUCT_FREE_CONTENTS_ONLY(asn_DEF_NR_DL_DCCH_Message, &dl_dcch_msg);
|
||||
LOG_D(NR_RRC, "DLInformationTransfer Encoded %zd bytes\n", r.encoded);
|
||||
// for (int i=0;i<encoded;i++) printf("%02x ",(*buffer)[i]);
|
||||
return (r.encoded + 7) / 8;
|
||||
return r.encoded;
|
||||
}
|
||||
|
||||
uint8_t do_NR_ULInformationTransfer(uint8_t **buffer, uint32_t pdu_length, uint8_t *pdu_buffer) {
|
||||
|
||||
@@ -2209,10 +2209,7 @@ NR_BCCH_DL_SCH_Message_t *get_SIB1_NR(const NR_ServingCellConfigCommon_t *scc, c
|
||||
AssertFatal(ServCellCom->tdd_UL_DL_ConfigurationCommon != NULL, "out of memory\n");
|
||||
ServCellCom->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing = scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
|
||||
ServCellCom->tdd_UL_DL_ConfigurationCommon->pattern1 = scc->tdd_UL_DL_ConfigurationCommon->pattern1;
|
||||
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
|
||||
ServCellCom->tdd_UL_DL_ConfigurationCommon->pattern2 = CALLOC(1, sizeof(struct NR_TDD_UL_DL_Pattern));
|
||||
*ServCellCom->tdd_UL_DL_ConfigurationCommon->pattern2 = *scc->tdd_UL_DL_ConfigurationCommon->pattern2;
|
||||
}
|
||||
ServCellCom->tdd_UL_DL_ConfigurationCommon->pattern2 = scc->tdd_UL_DL_ConfigurationCommon->pattern2;
|
||||
}
|
||||
ServCellCom->ss_PBCH_BlockPower = scc->ss_PBCH_BlockPower;
|
||||
|
||||
|
||||
@@ -27,7 +27,7 @@ metadata:
|
||||
spec:
|
||||
runPolicy: "Serial"
|
||||
nodeSelector:
|
||||
kubernetes.io/hostname: demophon
|
||||
kubernetes.io/hostname: theseus
|
||||
source:
|
||||
type: "Binary"
|
||||
strategy:
|
||||
|
||||
@@ -27,7 +27,7 @@ metadata:
|
||||
spec:
|
||||
runPolicy: "Serial"
|
||||
nodeSelector:
|
||||
kubernetes.io/hostname: demophon
|
||||
kubernetes.io/hostname: theseus
|
||||
source:
|
||||
type: "Binary"
|
||||
strategy:
|
||||
|
||||
@@ -269,20 +269,3 @@ int openair0_write_reorder(openair0_device *device, openair0_timestamp timestamp
|
||||
}
|
||||
return nsamps;
|
||||
}
|
||||
|
||||
void openair0_write_reorder_clear_context(openair0_device *device)
|
||||
{
|
||||
LOG_I(HW, "received write reorder clear context\n");
|
||||
re_order_t *ctx = &device->reOrder;
|
||||
if (!ctx->initDone)
|
||||
return;
|
||||
if (pthread_mutex_trylock(&ctx->mutex_write) == 0)
|
||||
LOG_E(HW, "write_reorder_clear_context call while still writing on the device\n");
|
||||
pthread_mutex_destroy(&ctx->mutex_write);
|
||||
pthread_mutex_lock(&ctx->mutex_store);
|
||||
for (int i = 0; i < WRITE_QUEUE_SZ; i++)
|
||||
ctx->queue[i].active = false;
|
||||
pthread_mutex_unlock(&ctx->mutex_store);
|
||||
pthread_mutex_destroy(&ctx->mutex_store);
|
||||
ctx->initDone = false;
|
||||
}
|
||||
|
||||
@@ -671,7 +671,7 @@ extern int read_recplayconfig(recplay_conf_t **recplay_conf, recplay_state_t **r
|
||||
extern void iqrecorder_end(openair0_device *device);
|
||||
|
||||
int openair0_write_reorder(openair0_device *device, openair0_timestamp timestamp, void **txp, int nsamps, int nbAnt, int flags);
|
||||
void openair0_write_reorder_clear_context(openair0_device *device);
|
||||
|
||||
#include <unistd.h>
|
||||
#ifndef gettid
|
||||
#define gettid() syscall(__NR_gettid)
|
||||
|
||||
Reference in New Issue
Block a user