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4 Commits
actor-cont
...
microamp_E
| Author | SHA1 | Date | |
|---|---|---|---|
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83d5255bb5 | ||
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6449c334be | ||
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de8b43bbe0 | ||
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7bae2fe095 |
@@ -83,8 +83,8 @@
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#define MAX_NUM_SLICES 1024
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// RLC Entity
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#define RLC_TX_MAXSIZE 10000000
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#define RLC_RX_MAXSIZE 10000000
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#define RLC_TX_MAXSIZE 1000000000
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#define RLC_RX_MAXSIZE 1000000000
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#define SEND_MRW_ON 240
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#define MAX_ANT 8
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// CBA constant
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@@ -214,6 +214,7 @@ static void rx_func(processingData_L1_t *info)
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gNB->if_inst->NR_UL_indication(&UL_INFO);
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stop_meas(&gNB->ul_indication_stats);
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if (IS_SOFTMODEM_RFSIM) {
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notifiedFIFO_elt_t *res = newNotifiedFIFO_elt(sizeof(processingData_L1_t), 0, &gNB->L1_rx_out, NULL);
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processingData_L1_t *syncMsg = NotifiedFifoData(res);
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syncMsg->gNB = gNB;
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@@ -222,6 +223,7 @@ static void rx_func(processingData_L1_t *info)
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res->key = slot_rx;
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LOG_D(NR_PHY, "Signaling completion for %d.%d (mod_slot %d) on L1_rx_out\n", frame_rx, slot_rx, slot_rx % RU_RX_SLOT_DEPTH);
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pushNotifiedFIFO(&gNB->L1_rx_out, res);
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}
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}
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}
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@@ -1192,7 +1192,7 @@ void *ru_thread(void *param)
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// do RX front-end processing (frequency-shift, dft) if needed
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int slot_type = nr_slot_select(&ru->config, proc->frame_rx, proc->tti_rx);
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if (slot_type == NR_UPLINK_SLOT || slot_type == NR_MIXED_SLOT) {
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if (!wait_free_rx_tti(&gNB->L1_rx_out, rx_tti_busy, proc->frame_rx, proc->tti_rx))
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if (IS_SOFTMODEM_RFSIM && !wait_free_rx_tti(&gNB->L1_rx_out, rx_tti_busy, proc->frame_rx, proc->tti_rx))
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break; // nothing to wait for: we have to stop
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if (ru->feprx) {
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ru->feprx(ru,proc->tti_rx);
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@@ -72,7 +72,7 @@ int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame, int slot, find_type_t type) {
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int nr_fill_prach(PHY_VARS_gNB *gNB, int SFN, int Slot, nfapi_nr_prach_pdu_t *prach_pdu)
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{
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int prach_id = find_nr_prach(gNB, SFN, Slot, SEARCH_EXIST_OR_FREE);
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AssertFatal(((prach_id >= 0) && (prach_id < NUMBER_OF_NR_PRACH_MAX)), "illegal or no prach_id found!!! prach_id %d\n", prach_id);
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//AssertFatal(((prach_id >= 0) && (prach_id < NUMBER_OF_NR_PRACH_MAX)), "illegal or no prach_id found!!! prach_id %d\n", prach_id);
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gNB_PRACH_list_t *prach = &gNB->prach_vars.list[prach_id];
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prach->frame = SFN;
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prach->slot = Slot;
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@@ -1000,7 +1000,9 @@ static NR_ServingCellConfigCommon_t *get_scc_config(configmodule_interface_t *cf
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LOG_I(RRC, "absoluteFrequencySSB %ld corresponds to %lu Hz\n", *frequencyInfoDL->absoluteFrequencySSB, ssb_freq);
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if (IS_SA_MODE(get_softmodem_params()))
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check_ssb_raster(ssb_freq, *frequencyInfoDL->frequencyBandList.list.array[0], *scc->ssbSubcarrierSpacing);
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LOG_I(RRC, "mjoang before ssb_bitmap 0x%" PRIX64 "\n", ssb_bitmap);
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fix_scc(scc, ssb_bitmap);
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LOG_I(RRC, "mjoang after ssb_bitmap 0x%" PRIX64 "\n", ssb_bitmap);
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}
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nr_rrc_config_ul_tda(scc, minRXTXTIME, do_SRS);
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@@ -804,192 +804,198 @@ static void nr_generate_Msg3_retransmission(module_id_t module_idP,
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uint16_t K2 = tda_info.k2 + get_NTN_Koffset(scc);
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const int sched_frame = (frame + (slot + K2) / slots_frame) % MAX_FRAME_NUMBER;
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const int sched_slot = (slot + K2) % slots_frame;
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uint16_t slot_bitmap = get_ul_bitmap(&nr_mac->frame_structure, sched_slot);
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uint16_t tda_bitmap = SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
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if (is_dl_slot(slot, &nr_mac->frame_structure) && is_ul_slot(sched_slot, &nr_mac->frame_structure)) {
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NR_beam_alloc_t beam_ul = beam_allocation_procedure(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame);
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if (beam_ul.idx < 0)
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return;
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NR_beam_alloc_t beam_dci = beam_allocation_procedure(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame);
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if (beam_dci.idx < 0) {
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reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
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return;
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}
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int buffer_index = ul_buffer_index(sched_frame, sched_slot, slots_frame, nr_mac->vrb_map_UL_size);
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uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam_ul.idx][buffer_index * MAX_BWP_SIZE];
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NR_pusch_dmrs_t dmrs_info = get_ul_dmrs_params(scc, ul_bwp, &tda_info, 1);
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int num_dmrs_symb = count_bits64_with_mask(dmrs_info.ul_dmrs_symb_pos, tda_info.startSymbolIndex, tda_info.nrOfSymbols);
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int TBS = 0, mcsindex = 0, R = 0, Qm = 0;
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while(TBS < 7) { // TBS for msg3 is 7 bytes (except for RRCResumeRequest1 currently not implemented)
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mcsindex++;
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AssertFatal(mcsindex <= 28, "Exceeding MCS limit for Msg3\n");
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R = nr_get_code_rate_ul(mcsindex, ul_bwp->mcs_table);
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Qm = nr_get_Qm_ul(mcsindex, ul_bwp->mcs_table);
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TBS = nr_compute_tbs(Qm,
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R,
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ra->msg3_nb_rb,
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tda_info.nrOfSymbols,
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num_dmrs_symb * 12, // nb dmrs set for no data in dmrs symbol
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0, //nb_rb_oh
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0, // to verify tb scaling
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1) >> 3;
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}
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if (!is_dl_slot(slot, &nr_mac->frame_structure)
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|| !is_ul_slot(sched_slot, &nr_mac->frame_structure)
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|| !((tda_bitmap & slot_bitmap) == tda_bitmap))
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return;
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NR_sched_pusch_t sched_pusch = {
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.bwp_info = get_pusch_bwp_start_size(UE),
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.tb_size = TBS,
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.rbSize = ra->msg3_nb_rb,
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.R = R,
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.Qm = Qm,
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.mcs = mcsindex,
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.nrOfLayers = 1,
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.tda_info = tda_info,
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.dmrs_info = dmrs_info,
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};
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int rbStart = 0;
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for (int i = 0; (i < ra->msg3_nb_rb) && (rbStart <= (sched_pusch.bwp_info.bwpSize - ra->msg3_nb_rb)); i++) {
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if (vrb_map_UL[rbStart + sched_pusch.bwp_info.bwpStart + i] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) {
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rbStart += i;
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i = 0;
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}
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}
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if (rbStart > (sched_pusch.bwp_info.bwpSize - ra->msg3_nb_rb)) {
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// cannot find free vrb_map for msg3 retransmission in this slot
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reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
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reset_beam_status(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame, beam_dci.new_beam);
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return;
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}
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sched_pusch.rbStart = rbStart;
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LOG_I(NR_MAC,
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"%4d%2d: RA RNTI %04x CC_id %d Scheduling retransmission of Msg3 in (%d,%d)\n",
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frame,
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slot,
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UE->rnti,
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CC_id,
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sched_frame,
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sched_slot);
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buffer_index = ul_buffer_index(sched_frame, sched_slot, slots_frame, nr_mac->UL_tti_req_ahead_size);
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nfapi_nr_ul_tti_request_t *future_ul_tti_req = &nr_mac->UL_tti_req_ahead[CC_id][buffer_index];
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AssertFatal(future_ul_tti_req->SFN == sched_frame
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&& future_ul_tti_req->Slot == sched_slot,
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"future UL_tti_req's frame.slot %d.%d does not match PUSCH %d.%d\n",
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future_ul_tti_req->SFN,
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future_ul_tti_req->Slot,
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sched_frame,
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sched_slot);
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AssertFatal(future_ul_tti_req->n_pdus <
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sizeof(future_ul_tti_req->pdus_list) / sizeof(future_ul_tti_req->pdus_list[0]),
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"Invalid future_ul_tti_req->n_pdus %d\n", future_ul_tti_req->n_pdus);
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future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
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future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
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nfapi_nr_pusch_pdu_t *pusch_pdu = prepare_pusch_pdu(future_ul_tti_req,
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UE,
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scc,
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&sched_pusch,
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get_transformPrecoding(ul_bwp, NR_UL_DCI_FORMAT_0_0, 0),
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0,
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ra->msg3_round,
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ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping,
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UE->rnti);
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future_ul_tti_req->n_pdus += 1;
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// generation of DCI 0_0 to schedule msg3 retransmission
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
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if (!pdcch_pdu_rel15) {
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nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
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memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
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ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
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ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
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pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
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ul_dci_req->numPdus += 1;
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nr_configure_pdcch(pdcch_pdu_rel15, coreset, &UE->UE_sched_ctrl.sched_pdcch);
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nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
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}
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uint8_t aggregation_level;
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int CCEIndex = get_cce_index(nr_mac,
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CC_id, slot, 0,
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&aggregation_level,
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beam_dci.idx,
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ss,
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coreset,
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&UE->UE_sched_ctrl.sched_pdcch,
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0);
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if (CCEIndex < 0) {
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LOG_E(NR_MAC, "UE %04x cannot find free CCE!\n", UE->rnti);
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reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
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reset_beam_status(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame, beam_dci.new_beam);
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return;
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}
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// Fill PDCCH DL DCI PDU
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nfapi_nr_dl_dci_pdu_t *dci_pdu = prepare_dci_pdu(pdcch_pdu_rel15,
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scc,
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ss,
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coreset,
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aggregation_level,
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CCEIndex,
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UE->UE_beam_index,
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UE->rnti);
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pdcch_pdu_rel15->numDlDci++;
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dci_pdu_rel15_t uldci_payload = {0};
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config_uldci(sc_info,
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pusch_pdu,
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&uldci_payload,
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NULL,
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NULL,
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ra->Msg3_tda_id,
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ra->msg3_TPC,
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1, // Not toggling NDI in msg3 retransmissions
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ul_bwp,
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ss->searchSpaceType->present);
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// Reset TPC to 0 dB to not request new gain multiple times before computing new value for SNR
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ra->msg3_TPC = 1;
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fill_dci_pdu_rel15(sc_info,
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&UE->current_DL_BWP,
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ul_bwp,
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dci_pdu,
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&uldci_payload,
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NR_UL_DCI_FORMAT_0_0,
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TYPE_TC_RNTI_,
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ul_bwp->bwp_id,
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ss,
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coreset,
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0, // parameter not needed for DCI 0_0
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nr_mac->cset0_bwp_size);
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// Mark the corresponding RBs as used
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fill_pdcch_vrb_map(nr_mac,
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CC_id,
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&UE->UE_sched_ctrl.sched_pdcch,
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CCEIndex,
|
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aggregation_level,
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beam_dci.idx);
|
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for (int rb = 0; rb < ra->msg3_nb_rb; rb++) {
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vrb_map_UL[rbStart + sched_pusch.bwp_info.bwpStart + rb] |= SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
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}
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|
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// Restart RA contention resolution timer in Msg3 retransmission slot (current slot + K2)
|
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// 3GPP TS 38.321 Section 5.1.5 Contention Resolution
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start_ra_contention_resolution_timer(
|
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ra,
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scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ra_ContentionResolutionTimer,
|
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K2,
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ul_bwp->scs);
|
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|
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// reset state to wait msg3
|
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ra->ra_state = nrRA_WAIT_Msg3;
|
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ra->Msg3_frame = sched_frame;
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ra->Msg3_slot = sched_slot;
|
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NR_beam_alloc_t beam_ul = beam_allocation_procedure(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame);
|
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if (beam_ul.idx < 0)
|
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return;
|
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NR_beam_alloc_t beam_dci = beam_allocation_procedure(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame);
|
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if (beam_dci.idx < 0) {
|
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reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
|
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return;
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}
|
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int buffer_index = ul_buffer_index(sched_frame, sched_slot, slots_frame, nr_mac->vrb_map_UL_size);
|
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uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam_ul.idx][buffer_index * MAX_BWP_SIZE];
|
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|
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NR_pusch_dmrs_t dmrs_info = get_ul_dmrs_params(scc, ul_bwp, &tda_info, 1);
|
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int num_dmrs_symb = count_bits64_with_mask(dmrs_info.ul_dmrs_symb_pos, tda_info.startSymbolIndex, tda_info.nrOfSymbols);
|
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int TBS = 0, mcsindex = 0, R = 0, Qm = 0;
|
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while(TBS < 7) { // TBS for msg3 is 7 bytes (except for RRCResumeRequest1 currently not implemented)
|
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mcsindex++;
|
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AssertFatal(mcsindex <= 28, "Exceeding MCS limit for Msg3\n");
|
||||
R = nr_get_code_rate_ul(mcsindex, ul_bwp->mcs_table);
|
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Qm = nr_get_Qm_ul(mcsindex, ul_bwp->mcs_table);
|
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TBS = nr_compute_tbs(Qm,
|
||||
R,
|
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ra->msg3_nb_rb,
|
||||
tda_info.nrOfSymbols,
|
||||
num_dmrs_symb * 12, // nb dmrs set for no data in dmrs symbol
|
||||
0, //nb_rb_oh
|
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0, // to verify tb scaling
|
||||
1) >> 3;
|
||||
}
|
||||
|
||||
NR_sched_pusch_t sched_pusch = {
|
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.bwp_info = get_pusch_bwp_start_size(UE),
|
||||
.tb_size = TBS,
|
||||
.rbSize = ra->msg3_nb_rb,
|
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.R = R,
|
||||
.Qm = Qm,
|
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.mcs = mcsindex,
|
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.nrOfLayers = 1,
|
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.tda_info = tda_info,
|
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.dmrs_info = dmrs_info,
|
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};
|
||||
|
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int rbStart = 0;
|
||||
for (int i = 0; (i < ra->msg3_nb_rb) && (rbStart <= (sched_pusch.bwp_info.bwpSize - ra->msg3_nb_rb)); i++) {
|
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if (vrb_map_UL[rbStart + sched_pusch.bwp_info.bwpStart + i] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) {
|
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rbStart += i;
|
||||
i = 0;
|
||||
}
|
||||
}
|
||||
if (rbStart > (sched_pusch.bwp_info.bwpSize - ra->msg3_nb_rb)) {
|
||||
// cannot find free vrb_map for msg3 retransmission in this slot
|
||||
reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
|
||||
reset_beam_status(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame, beam_dci.new_beam);
|
||||
return;
|
||||
}
|
||||
|
||||
sched_pusch.rbStart = rbStart;
|
||||
LOG_I(NR_MAC,
|
||||
"%4d%2d: RA RNTI %04x CC_id %d Scheduling retransmission of Msg3 in (%d,%d)\n",
|
||||
frame,
|
||||
slot,
|
||||
UE->rnti,
|
||||
CC_id,
|
||||
sched_frame,
|
||||
sched_slot);
|
||||
|
||||
buffer_index = ul_buffer_index(sched_frame, sched_slot, slots_frame, nr_mac->UL_tti_req_ahead_size);
|
||||
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &nr_mac->UL_tti_req_ahead[CC_id][buffer_index];
|
||||
AssertFatal(future_ul_tti_req->SFN == sched_frame
|
||||
&& future_ul_tti_req->Slot == sched_slot,
|
||||
"future UL_tti_req's frame.slot %d.%d does not match PUSCH %d.%d\n",
|
||||
future_ul_tti_req->SFN,
|
||||
future_ul_tti_req->Slot,
|
||||
sched_frame,
|
||||
sched_slot);
|
||||
AssertFatal(future_ul_tti_req->n_pdus <
|
||||
sizeof(future_ul_tti_req->pdus_list) / sizeof(future_ul_tti_req->pdus_list[0]),
|
||||
"Invalid future_ul_tti_req->n_pdus %d\n", future_ul_tti_req->n_pdus);
|
||||
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
|
||||
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
|
||||
nfapi_nr_pusch_pdu_t *pusch_pdu = prepare_pusch_pdu(future_ul_tti_req,
|
||||
UE,
|
||||
scc,
|
||||
&sched_pusch,
|
||||
get_transformPrecoding(ul_bwp, NR_UL_DCI_FORMAT_0_0, 0),
|
||||
0,
|
||||
ra->msg3_round,
|
||||
ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping,
|
||||
UE->rnti);
|
||||
future_ul_tti_req->n_pdus += 1;
|
||||
|
||||
// generation of DCI 0_0 to schedule msg3 retransmission
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
|
||||
if (!pdcch_pdu_rel15) {
|
||||
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
|
||||
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
|
||||
ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
|
||||
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
|
||||
pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
|
||||
ul_dci_req->numPdus += 1;
|
||||
nr_configure_pdcch(pdcch_pdu_rel15, coreset, &UE->UE_sched_ctrl.sched_pdcch);
|
||||
nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
|
||||
}
|
||||
|
||||
uint8_t aggregation_level;
|
||||
int CCEIndex = get_cce_index(nr_mac,
|
||||
CC_id, slot, 0,
|
||||
&aggregation_level,
|
||||
beam_dci.idx,
|
||||
ss,
|
||||
coreset,
|
||||
&UE->UE_sched_ctrl.sched_pdcch,
|
||||
0);
|
||||
if (CCEIndex < 0) {
|
||||
LOG_E(NR_MAC, "UE %04x cannot find free CCE!\n", UE->rnti);
|
||||
reset_beam_status(&nr_mac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_frame, beam_ul.new_beam);
|
||||
reset_beam_status(&nr_mac->beam_info, frame, slot, UE->UE_beam_index, slots_frame, beam_dci.new_beam);
|
||||
return;
|
||||
}
|
||||
|
||||
// Fill PDCCH DL DCI PDU
|
||||
nfapi_nr_dl_dci_pdu_t *dci_pdu = prepare_dci_pdu(pdcch_pdu_rel15,
|
||||
scc,
|
||||
ss,
|
||||
coreset,
|
||||
aggregation_level,
|
||||
CCEIndex,
|
||||
UE->UE_beam_index,
|
||||
UE->rnti);
|
||||
pdcch_pdu_rel15->numDlDci++;
|
||||
|
||||
dci_pdu_rel15_t uldci_payload = {0};
|
||||
config_uldci(sc_info,
|
||||
pusch_pdu,
|
||||
&uldci_payload,
|
||||
NULL,
|
||||
NULL,
|
||||
ra->Msg3_tda_id,
|
||||
ra->msg3_TPC,
|
||||
1, // Not toggling NDI in msg3 retransmissions
|
||||
ul_bwp,
|
||||
ss->searchSpaceType->present);
|
||||
|
||||
// Reset TPC to 0 dB to not request new gain multiple times before computing new value for SNR
|
||||
ra->msg3_TPC = 1;
|
||||
|
||||
fill_dci_pdu_rel15(sc_info,
|
||||
&UE->current_DL_BWP,
|
||||
ul_bwp,
|
||||
dci_pdu,
|
||||
&uldci_payload,
|
||||
NR_UL_DCI_FORMAT_0_0,
|
||||
TYPE_TC_RNTI_,
|
||||
ul_bwp->bwp_id,
|
||||
ss,
|
||||
coreset,
|
||||
0, // parameter not needed for DCI 0_0
|
||||
nr_mac->cset0_bwp_size);
|
||||
|
||||
// Mark the corresponding RBs as used
|
||||
|
||||
fill_pdcch_vrb_map(nr_mac,
|
||||
CC_id,
|
||||
&UE->UE_sched_ctrl.sched_pdcch,
|
||||
CCEIndex,
|
||||
aggregation_level,
|
||||
beam_dci.idx);
|
||||
|
||||
for (int rb = 0; rb < ra->msg3_nb_rb; rb++) {
|
||||
vrb_map_UL[rbStart + sched_pusch.bwp_info.bwpStart + rb] |= SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
|
||||
}
|
||||
|
||||
// Restart RA contention resolution timer in Msg3 retransmission slot (current slot + K2)
|
||||
// 3GPP TS 38.321 Section 5.1.5 Contention Resolution
|
||||
start_ra_contention_resolution_timer(
|
||||
ra,
|
||||
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ra_ContentionResolutionTimer,
|
||||
K2,
|
||||
ul_bwp->scs);
|
||||
|
||||
// reset state to wait msg3
|
||||
ra->ra_state = nrRA_WAIT_Msg3;
|
||||
ra->Msg3_frame = sched_frame;
|
||||
ra->Msg3_slot = sched_slot;
|
||||
}
|
||||
|
||||
static bool get_feasible_msg3_tda(const NR_ServingCellConfigCommon_t *scc,
|
||||
@@ -1013,6 +1019,7 @@ static bool get_feasible_msg3_tda(const NR_ServingCellConfigCommon_t *scc,
|
||||
int abs_slot = slot + k2 + mu_delta;
|
||||
int temp_frame = (frame + (abs_slot / slots_per_frame)) & 1023;
|
||||
int temp_slot = abs_slot % slots_per_frame; // msg3 slot according to 8.3 in 38.213
|
||||
LOG_D(NR_MAC, "Checking Msg3 TDA %d: k2 %ld => slot %d.%d\n", i, k2, temp_frame, temp_slot);
|
||||
if (fs->frame_type == TDD && !is_ul_slot(temp_slot, fs))
|
||||
continue;
|
||||
|
||||
@@ -1028,7 +1035,7 @@ static bool get_feasible_msg3_tda(const NR_ServingCellConfigCommon_t *scc,
|
||||
/* if this start and length of this TDA cannot be fulfilled, skip */
|
||||
if ((slot_mask & msg3_mask) != msg3_mask)
|
||||
continue;
|
||||
|
||||
LOG_D(NR_MAC, "Feasible Msg3 TDA %d found for slot %d.%d\n", i, temp_frame, temp_slot);
|
||||
// check if it is possible to allocate MSG3 in a beam in this slot
|
||||
NR_beam_alloc_t beam = beam_allocation_procedure(beam_info, temp_frame, temp_slot, ue_beam_idx, slots_per_frame);
|
||||
if (beam.idx < 0)
|
||||
@@ -1422,6 +1429,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
|
||||
if (!is_dl_slot(slotP, &nr_mac->frame_structure)) {
|
||||
return;
|
||||
}
|
||||
LOG_I(NR_MAC, "Generating Msg2 for UE RA-RNTI %04x TC-RNTI %04x at %d.%d\n", UE->ra->RA_rnti, UE->rnti, frameP, slotP);
|
||||
|
||||
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
|
||||
NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP;
|
||||
@@ -1442,9 +1450,18 @@ static void nr_generate_Msg2(module_id_t module_idP,
|
||||
LOG_E(NR_MAC, "UE RA-RNTI %04x TC-RNTI %04x: Msg2 not monitored by UE\n", ra->RA_rnti, UE->rnti);
|
||||
return;
|
||||
}
|
||||
LOG_D(NR_MAC, "UE RA-RNTI %04x TC-RNTI %04x: Msg2 monitored by UE at %d.%d\n", ra->RA_rnti, UE->rnti, frameP, slotP);
|
||||
NR_beam_alloc_t beam = beam_allocation_procedure(&nr_mac->beam_info, frameP, slotP, UE->UE_beam_index, n_slots_frame);
|
||||
if (beam.idx < 0)
|
||||
return;
|
||||
LOG_D(NR_MAC,
|
||||
"UE RA-RNTI %04x TC-RNTI %04x: Msg2 will be sent using beam %d (new beam %d) at %d.%d\n",
|
||||
ra->RA_rnti,
|
||||
UE->rnti,
|
||||
beam.idx,
|
||||
beam.new_beam,
|
||||
frameP,
|
||||
slotP);
|
||||
|
||||
const NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
|
||||
bool ret = get_feasible_msg3_tda(scc,
|
||||
@@ -1457,7 +1474,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
|
||||
UE->UE_beam_index,
|
||||
&nr_mac->frame_structure);
|
||||
if (!ret || ra->Msg3_tda_id > 15) {
|
||||
LOG_D(NR_MAC, "UE RNTI %04x %d.%d: infeasible Msg3 TDA\n", UE->rnti, frameP, slotP);
|
||||
LOG_E(NR_MAC, "UE RNTI %04x %d.%d: infeasible Msg3 TDA\n", UE->rnti, frameP, slotP);
|
||||
reset_beam_status(&nr_mac->beam_info, frameP, slotP, UE->UE_beam_index, n_slots_frame, beam.new_beam);
|
||||
return;
|
||||
}
|
||||
@@ -1738,6 +1755,7 @@ static void nr_generate_Msg4_MsgB(module_id_t module_idP,
|
||||
coreset->controlResourceSetId,
|
||||
false);
|
||||
if (!msg4_tda.valid_tda) {
|
||||
LOG_I(NR_MAC, "msg4_tda.valid_tda\n");
|
||||
reset_beam_status(&nr_mac->beam_info, frameP, slotP, UE->UE_beam_index, n_slots_frame, beam.new_beam);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -789,6 +789,7 @@ static void pf_dl(module_id_t module_id,
|
||||
while (rbStart + max_rbSize <= rbStop && !(rballoc_mask[rbStart + max_rbSize + bwp_start] & slbitmap))
|
||||
max_rbSize++;
|
||||
|
||||
|
||||
if (max_rbSize < min_rbSize) {
|
||||
LOG_D(NR_MAC,
|
||||
"(%d.%d) Cannot schedule RNTI %04x, rbStart %d, rbSize %d, rbStop %d\n",
|
||||
@@ -1023,6 +1024,12 @@ void nr_schedule_ue_spec(module_id_t module_id,
|
||||
|
||||
if (!is_dl_slot(slot, &gNB_mac->frame_structure))
|
||||
return;
|
||||
|
||||
if (gNB_mac->type0_PDCCH_CSS_config[2].active == true)
|
||||
{
|
||||
LOG_D(NR_MAC,"skip %d.%d\n",frame, slot);
|
||||
return;
|
||||
}
|
||||
|
||||
/* PREPROCESSOR */
|
||||
gNB_mac->pre_processor_dl(module_id, frame, slot);
|
||||
|
||||
@@ -279,7 +279,7 @@ void nr_csi_meas_reporting(int Mod_idP,frame_t frame, slot_t slot)
|
||||
|
||||
const int pucch_index = get_pucch_index(sched_frame, sched_slot, &nrmac->frame_structure, sched_ctrl->sched_pucch_size);
|
||||
NR_sched_pucch_t *curr_pucch = &sched_ctrl->sched_pucch[pucch_index];
|
||||
AssertFatal(curr_pucch->active == false, "CSI structure is scheduled in advance. It should be free!\n");
|
||||
//AssertFatal(curr_pucch->active == false, "CSI structure is scheduled in advance. It should be free!\n");
|
||||
curr_pucch->r_pucch = -1;
|
||||
curr_pucch->frame = sched_frame;
|
||||
curr_pucch->ul_slot = sched_slot;
|
||||
@@ -1145,8 +1145,8 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
|
||||
|
||||
const int minfbtime = mac->radio_config.minRXTXTIME + NTN_gNB_Koffset;
|
||||
const NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
|
||||
const int n_slots_frame = mac->frame_structure.numb_slots_frame;
|
||||
const frame_structure_t *fs = &mac->frame_structure;
|
||||
const int n_slots_frame = fs->numb_slots_frame;
|
||||
|
||||
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
|
||||
NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config;
|
||||
@@ -1168,9 +1168,12 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
|
||||
const int pucch_slot = (slot + pdsch_to_harq_feedback[f] + NTN_gNB_Koffset) % n_slots_frame;
|
||||
// check if the slot is UL
|
||||
if (fs->frame_type == TDD) {
|
||||
int mod_slot = pucch_slot % fs->numb_slots_period;
|
||||
int mod_slot = get_slot_idx_in_period(pucch_slot, fs);
|
||||
if (!is_ul_slot(mod_slot, fs))
|
||||
continue;
|
||||
const tdd_period_config_t *pc = &fs->period_cfg;
|
||||
if (r_pucch >= 0 && is_mixed_slot(mod_slot, fs) && pc->tdd_slot_bitmap[mod_slot].num_ul_symbols < 2)
|
||||
continue;
|
||||
}
|
||||
const int pucch_frame = (frame + ((slot + pdsch_to_harq_feedback[f] + NTN_gNB_Koffset) / n_slots_frame)) % MAX_FRAME_NUMBER;
|
||||
// we store PUCCH resources according to slot, TDD configuration and size of the vector containing PUCCH structures
|
||||
|
||||
@@ -38,6 +38,15 @@
|
||||
|
||||
//#define SRS_IND_DEBUG
|
||||
|
||||
uint16_t get_ul_bitmap(const frame_structure_t *fs, int slot)
|
||||
{
|
||||
const int slot_period = slot % fs->numb_slots_period;
|
||||
const tdd_bitmap_t *bm = &fs->period_cfg.tdd_slot_bitmap[slot_period];
|
||||
/* For some reason, we only store the number of symbols if it's mixed */
|
||||
const int num_ul_symbols = bm->slot_type == TDD_NR_MIXED_SLOT ? bm->num_ul_symbols : 14;
|
||||
return SL_to_bitmap(14 - num_ul_symbols, num_ul_symbols);
|
||||
}
|
||||
|
||||
/* \brief Get the number of UL TDAs that could be used in slot, reachable
|
||||
* via specific k2. The output parameter first_idx is a pointer to the first
|
||||
* suitable TDA, and the function returns the number of suitable TDAs, or 0. */
|
||||
@@ -46,13 +55,7 @@ int get_num_ul_tda(gNB_MAC_INST *nrmac, int slot, int k2, const NR_tda_info_t **
|
||||
/* we assume that this function is mutex-protected from outside */
|
||||
NR_SCHED_ENSURE_LOCKED(&nrmac->sched_lock);
|
||||
|
||||
const frame_structure_t *fs = &nrmac->frame_structure;
|
||||
const int slot_period = slot % fs->numb_slots_period;
|
||||
const tdd_bitmap_t *bm = &fs->period_cfg.tdd_slot_bitmap[slot_period];
|
||||
/* For some reason, we only store the number of symbols if it's mixed */
|
||||
const int num_ul_symbols = bm->slot_type == TDD_NR_MIXED_SLOT ? bm->num_ul_symbols : 14;
|
||||
const uint16_t ul_bitmap = SL_to_bitmap(14 - num_ul_symbols, num_ul_symbols);
|
||||
|
||||
const uint16_t ul_bitmap = get_ul_bitmap(&nrmac->frame_structure, slot);
|
||||
*first_idx = NULL;
|
||||
FOR_EACH_SEQ_ARR(NR_tda_info_t *, tda, &nrmac->ul_tda) {
|
||||
DevAssert(tda->valid_tda);
|
||||
|
||||
@@ -47,7 +47,7 @@ int get_dl_slots_per_period(const frame_structure_t *fs);
|
||||
int get_full_ul_slots_per_period(const frame_structure_t *fs);
|
||||
int get_full_dl_slots_per_period(const frame_structure_t *fs);
|
||||
int get_ul_slot_offset(const frame_structure_t *fs, int idx, bool count_mixed);
|
||||
|
||||
uint16_t get_ul_bitmap(const frame_structure_t *fs, int slot);
|
||||
void delete_nr_ue_data(NR_UE_info_t *UE, NR_COMMON_channels_t *ccPtr, uid_allocator_t *uia);
|
||||
|
||||
void mac_top_init_gNB(ngran_node_t node_type,
|
||||
|
||||
@@ -17,7 +17,7 @@ add_library(oran_fhlib_5g MODULE
|
||||
)
|
||||
|
||||
set(E_VERSION 5.1.6)
|
||||
set(F_VERSION 6.1.5)
|
||||
set(F_VERSION 6.1.4)
|
||||
|
||||
find_package(xran REQUIRED)
|
||||
if(xran_VERSION VERSION_EQUAL E_VERSION)
|
||||
|
||||
Reference in New Issue
Block a user