feat(vrtsim): Add emulator mode

The emulator mode allows to emulate real time RF.

ci-scripts/xml_files/gnb_usrp_build.xml

@@ -40,7 +40,7 @@
 		<mode>TesteNB</mode>	
 		<class>Build_eNB</class>
 		<desc>Build gNB (USRP)</desc>
-		<Build_eNB_args>--gNB -w USRP --ninja -c -P --build-lib ldpc_cuda --build-lib ldpc_t2 --cmake-opt -DASN1C_EXEC=/opt/asn1c/bin/asn1c</Build_eNB_args>
+		<Build_eNB_args>--gNB -w USRP --ninja -c -P --build-lib ldpc_cuda --build-lib ldpc_aal --cmake-opt -DASN1C_EXEC=/opt/asn1c/bin/asn1c</Build_eNB_args>
 		<forced_workspace_cleanup>True</forced_workspace_cleanup>
 	</testCase>
 

ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml

@@ -62,7 +62,7 @@
 		<always_exec>true</always_exec>
 		<physim_test>nr_ulsim</physim_test>
 		<physim_time_threshold>100</physim_time_threshold>
-		<physim_run_args>-n1000 -s30 -S30.2 -m5 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+		<physim_run_args>-n1000 -s30 -S30.2 -m5 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="010121">
@@ -80,7 +80,7 @@
 		<always_exec>true</always_exec>
 		<physim_test>nr_ulsim</physim_test>
 		<physim_time_threshold>150</physim_time_threshold>
-		<physim_run_args>-n1000 -s30 -S30.2 -m15 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+		<physim_run_args>-n1000 -s30 -S30.2 -m15 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="010131">
@@ -98,7 +98,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>250</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="010211">
@@ -116,7 +116,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>150</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="010221">
@@ -134,7 +134,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>350</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="010231">
@@ -152,7 +152,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>550</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="010311">
@@ -170,7 +170,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>250</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="010321">
@@ -188,7 +188,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>650</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="010331">
@@ -206,7 +206,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_ulsim</physim_test>
                 <physim_time_threshold>1100</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
 </testCaseList>

ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml

@@ -63,7 +63,7 @@
 		<always_exec>true</always_exec>
 		<physim_test>nr_dlsim</physim_test>
 		<physim_time_threshold>100</physim_time_threshold>
-		<physim_run_args>-n1000 -s30 -S30.2 -e5 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+		<physim_run_args>-n1000 -s30 -S30.2 -e5 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="000121">
@@ -81,7 +81,7 @@
 		<always_exec>true</always_exec>
 		<physim_test>nr_dlsim</physim_test>
 		<physim_time_threshold>100</physim_time_threshold>
-		<physim_run_args>-n1000 -s30 -S30.2 -e15 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+		<physim_run_args>-n1000 -s30 -S30.2 -e15 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="000131">
@@ -99,7 +99,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>200</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000211">
@@ -117,7 +117,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>150</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
 	</testCase>
 
 	<testCase id="000221">
@@ -135,7 +135,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>250</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000231">
@@ -153,7 +153,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>400</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000311">
@@ -171,7 +171,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>200</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000321">
@@ -189,7 +189,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>500</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000331">
@@ -207,7 +207,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>500</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000411">
@@ -225,7 +225,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>200</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000421">
@@ -243,7 +243,7 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>300</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 
         <testCase id="000431">
@@ -261,6 +261,6 @@
                 <always_exec>true</always_exec>
                 <physim_test>nr_dlsim</physim_test>
                 <physim_time_threshold>450</physim_time_threshold>
-                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12</physim_run_args>
+                <physim_run_args>-n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev d8:00.0 --nrLDPC_coding_aal.dpdk_core_list 11-12 --nrLDPC_coding_aal.is_t2 1</physim_run_args>
         </testCase>
 </testCaseList>

cmake_targets/build_oai

@@ -46,7 +46,7 @@ BUILD_DOXYGEN=0
 DISABLE_HARDWARE_DEPENDENCY="False"
 CMAKE_BUILD_TYPE="RelWithDebInfo"
 CMAKE_CMD="$CMAKE"
-OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope ldpc_cuda ldpc_t2 ldpc_xdma websrv oai_iqplayer imscope imscope_record"
+OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope ldpc_cuda ldpc_aal ldpc_xdma websrv oai_iqplayer imscope imscope_record"
 TARGET_LIST=""
 BUILD_TOOL_OPT="-j$(nproc)"
 

common/utils/shm_iq_channel/shm_td_iq_channel.c

@@ -108,6 +108,50 @@ ShmTDIQChannel *shm_td_iq_channel_create(const char *name, int num_tx_ant, int n
   return channel;
 }
 
+ShmTDIQChannel *shm_td_iq_channel_emulator_create(const char *name, int num_tx_ant, int num_rx_ant)
+{
+  // Create memory segment
+  size_t tx_buffer_size = CIRCULAR_BUFFER_SIZE * sizeof(sample_t) * num_tx_ant;
+  size_t rx_buffer_size = CIRCULAR_BUFFER_SIZE * sizeof(sample_t) * num_rx_ant;
+  size_t total_size = sizeof(ShmTDIQChannelData) + tx_buffer_size + rx_buffer_size;
+  ShmTDIQChannelData *shm_ptr = (ShmTDIQChannelData *)malloc(total_size);
+
+  // Initialize shared memory
+  memset(shm_ptr, 0, total_size);
+  shm_ptr->num_antennas_tx = num_tx_ant;
+  shm_ptr->num_antennas_rx = num_rx_ant;
+  shm_ptr->is_connected = false;
+  ShmTDIQChannel *channel = calloc_or_fail(1, sizeof(ShmTDIQChannel));
+  strncpy(channel->name, name, sizeof(channel->name) - 1);
+  channel->tx_iq_data = (sample_t *)(shm_ptr + 1);
+  channel->rx_iq_data = channel->tx_iq_data + tx_buffer_size / sizeof(sample_t);
+  channel->data = shm_ptr;
+  channel->type = IQ_CHANNEL_TYPE_SERVER;
+  channel->last_timestamp = 0;
+  pthread_mutexattr_t mutex_attr;
+  pthread_condattr_t cond_attr;
+  int ret = pthread_mutexattr_init(&mutex_attr);
+  AssertFatal(ret == 0, "pthread_mutexattr_init() failed: errno %d, %s\n", errno, strerror(errno));
+
+  ret = pthread_condattr_init(&cond_attr);
+  AssertFatal(ret == 0, "pthread_condattr_init() failed: errno %d, %s\n", errno, strerror(errno));
+
+  ret = pthread_mutexattr_setpshared(&mutex_attr, PTHREAD_PROCESS_SHARED);
+  AssertFatal(ret == 0, "pthread_mutexattr_setpshared() failed: errno %d, %s\n", errno, strerror(errno));
+
+  ret = pthread_condattr_setpshared(&cond_attr, PTHREAD_PROCESS_SHARED);
+  AssertFatal(ret == 0, "pthread_condattr_setpshared() failed: errno %d, %s\n", errno, strerror(errno));
+
+  ret = pthread_mutex_init(&shm_ptr->mutex, &mutex_attr);
+  AssertFatal(ret == 0, "pthread_mutex_init() failed: errno %d, %s\n", errno, strerror(errno));
+
+  ret = pthread_cond_init(&shm_ptr->cond, &cond_attr);
+  AssertFatal(ret == 0, "pthread_cond_init() failed: errno %d, %s\n", errno, strerror(errno));
+
+  shm_ptr->magic = SHM_MAGIC_NUMBER;
+  return channel;
+}
+
 ShmTDIQChannel *shm_td_iq_channel_connect(const char *name, int timeout_in_seconds)
 {
   // Create shared memory segment
@@ -272,6 +316,11 @@ bool shm_td_iq_channel_is_connected(const ShmTDIQChannel *channel)
   return channel->data->is_connected;
 }
 
+void shm_td_iq_channel_emulator_connect(const ShmTDIQChannel *channel)
+{
+  channel->data->is_connected = true;
+}
+
 void shm_td_iq_channel_destroy(ShmTDIQChannel *channel)
 {
   ShmTDIQChannelData *data = channel->data;

common/utils/shm_iq_channel/shm_td_iq_channel.h

@@ -64,6 +64,16 @@ typedef struct ShmTDIQChannel_s ShmTDIQChannel;
  */
 ShmTDIQChannel *shm_td_iq_channel_create(const char *name, int num_tx_ant, int num_rx_ant);
 
+/**
+ * @brief Allocate an emulated IQ channel.
+ *
+ * @param name The name of the channel.
+ * @param num_tx_ant The number of TX antennas.
+ * @param num_rx_ant The number of RX antennas.
+ * @return A pointer to the created ShmTDIQChannel structure.
+ */
+ShmTDIQChannel *shm_td_iq_channel_emulator_create(const char *name, int num_tx_ant, int num_rx_ant);
+
 /**
  * @brief Connects to an existing shared memory IQ channel.
  *
@@ -129,6 +139,13 @@ void shm_td_iq_channel_wait(ShmTDIQChannel *channel, uint64_t timestamp);
  */
 bool shm_td_iq_channel_is_connected(const ShmTDIQChannel *channel);
 
+/**
+ * @brief Emulate IQ channel connection to enable RF emulation.
+ *
+ * @param channel The ShmTDIQChannel structure.
+ */
+void shm_td_iq_channel_emulator_connect(const ShmTDIQChannel *channel);
+
 /**
  * @brief Destroys the shared memory IQ channel.
  *

doc/BUILD.md

@@ -185,7 +185,7 @@ Some libraries have further dependencies and might not build on every system:
 - `enbscope`, `uescope`, `nrscope`: libforms/X
 - `ldpc_cuda`: CUDA
 - `websrv`: npm and others
-- `ldpc_t2`: DPDK with patch
+- `ldpc_aal`: DPDK with patch
 
 # Running `cmake` directly
 

doc/LDPC_OFFLOAD_SETUP.md

@@ -0,0 +1,344 @@
+<table style="border-collapse: collapse; border: none;">
+  <tr style="border-collapse: collapse; border: none;">
+    <td style="border-collapse: collapse; border: none;">
+      <a href="http://www.openairinterface.org/">
+         <img src="./images/oai_final_logo.png" alt="" border=3 height=50 width=150>
+         </img>
+      </a>
+    </td>
+    <td style="border-collapse: collapse; border: none; vertical-align: center;">
+      <b><font size = "5">OAI LDPC offload (O-RAN AAL/DPDK BBDEV)</font></b>
+    </td>
+  </tr>
+</table>
+
+**Table of Contents**
+
+[[_TOC_]]
+
+This documentation describes the integration of LDPC coding for lookaside acceleration using O-RAN AAL/DPDK BBDEV in OAI, along with its usage.
+For details on the implementation, please consult the [developer notes](../openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/README.md).
+
+# Requirements
+
+In principle, any lookaside LDPC accelerator supporting the O-RAN AAL/DPDK BBDEV should work.
+However, the current implementation has only been validated for the Xilinx T2, Intel ACC100, and Intel ACC200 (VRB1).
+Therefore, your mileage may vary when using other BBDEV devices as there may be some hardware-specific changes required -- contributions are welcome!
+
+## DPDK Version Requirements
+
+The following DPDK versions are supported:
+- For the Xilinx T2 card, DPDK20.11+ is supported.
+- As for the Intel ACC100/ACC200, only DPDK22.11+ is supported.
+
+## Tested Devices/ DPDK versions
+
+### Xilinx T2
+
+- DPDK20.11.9*.
+- DPDK22.11.7*.
+> Note: FPGA bitstream image and the corresponding patch file (e.g., `ACCL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch` for DPDK20.11) from Accelercomm required.
+
+### Intel ACC100
+
+- DPDK22.11.7*.
+- DPDK23.11.3*.
+- DPDK24.11.2.
+> Note: [Patch]((https://github.com/DPDK/dpdk/commit/fdde63a1dfc129d0a510a831aa98253b36a2a1cd)) required for pre-DPDK24.11 versions when using the Intel ACC100.
+
+### Intel ACC200 (also known as VRB1)
+- DPDK22.11.7.
+- DPDK23.11.3.
+- DPDK24.11.2.
+
+# System Setup
+## DPDK installation
+
+> Important: 
+> - If you are using the Xilinx T2 card, you will need to apply the vendor-supplied patches before compiling DPDK. 
+> - If you are using the Intel ACC100, you will need to [patch](https://github.com/DPDK/dpdk/commit/fdde63a1dfc129d0a510a831aa98253b36a2a1cd) the ACC100's driver if you are using DPDK22.11 or DPDK23.11. 
+
+
+Refer to the guide [here](./ORAN_FHI7.2_Tutorial.md?ref_type=heads#dpdk-data-plane-development-kit) to install, and then validate your DPDK installation.
+
+<details open> 
+<summary> Notes on DPDK patching/installation for Xilinx T2. </summary>
+
+*Note: The following instructions apply to `ACCL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch`, compatible with DPDK 20.11.9. For older patches (e.g., `ACL_BBDEV_DPDK20.11.3_BL_1006_build_1105_dev_branch_MCT_optimisations_1106_physical_std.patch`), refer to the T2 documentation in `2023.w48`.*
+
+```bash
+# Get DPDK source code
+git clone https://github.com/DPDK/dpdk-stable.git ~/dpdk-stable
+cd ~/dpdk-stable
+git checkout v20.11.9
+git apply ~/ACL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch
+```
+Replace `~/ACL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch` by patch file provided by
+Accelercomm.
+
+If you would like to install DPDK to a custom directory, here is an example.
+```bash
+cd ~/dpdk-stable
+# meson setup build
+meson setup --prefix=/opt/dpdk-t2 build # for installation with non-default installation prefix
+cd build
+ninja
+sudo ninja install
+sudo ldconfig
+
+```
+</details>
+
+## System configuration
+
+### Setting up Hugepages
+
+First, we must setup hugepages on the system.
+In our setup, we setup 16 of the 1G hugepages.
+Apart from 1G, 2MB hugepages works too, but make sure to allocate a sufficient number of them.
+
+```
+# sudo dpdk-hugepages.py -p 1G --setup 16G
+```
+
+### Locating the Accelerator
+
+Next, we check whether our system can detect our accelerator using `dpdk-devbind.py`.
+You should see Baseband devices detected by DPDK, as follows:
+```
+# sudo dpdk-devbind.py -s
+...
+Baseband devices using DPDK-compatible driver
+=============================================
+0000:f7:00.0 'Device 57c0' unused=vfio-pci
+...
+```
+
+As you can see here, our Intel ACC200 has the address of `0000:f7:00.0`.
+Depending on the accelerator you are using, the address may vary.
+
+### Loading VFIO-PCI and enabling SR-IOV
+Following, make sure to load the `vfio-pci` kernel modules and ensure that SR-IOV is enabled.
+
+```
+# sudo modprobe vfio-pci enable_sriov=1 disable_idle_d3=1
+```
+
+### Binding the Accelerator with `vfio-pci`
+
+Lastly, we bind our accelerator with the `vfio-pci` driver.
+```
+# sudo dpdk-devbind.py --bind=vfio-pci 0000:f7:00.0
+```
+
+> Note: For the Xilinx T2, we can use this device directly.
+If you use an Intel vRAN accelerator, read on.
+
+### Additional Steps for Intel vRAN Accelerators
+
+> IMPORTANT NOTE: 
+> - Currently, we only support using the Virtual Functions (VFs) of the Intel vRAN accelerators, but not the Physical Function (PF). 
+> - One key advantage of using VFs is that this allows us to share the accelerator with other DU instances on the same machine, which is common in practice.
+
+If you are using an Intel vRAN accelerator, you will need to use the [pf_bb_config](https://github.com/intel/pf-bb-config) tool to configure the accelerator beforehand. 
+
+#### pf_bb_config
+For more details, please consult the `pf_bb_config` README.
+
+```
+# git clone https://github.com/intel/pf-bb-config
+# cd ~/pf-bb-config
+# ./build.sh
+```
+This clones and builds the `pf_bb_config` binary.
+
+Next, we show an example for the Intel ACC200.
+We use an existing configuration located at `./vrb1/vrb1_config_16vf.cfg`.
+
+Here, it is necessary to specify a VFIO token (in this case, we use the UUID `00112233-4455-6677-8899-aabbccddeeff`).
+Note that in practice, a random UUID should be used.
+```
+# sudo ./pf_bb_config VRB1 -v 00112233-4455-6677-8899-aabbccddeeff -c vrb1/vrb1_config_16vf.cfg
+== pf_bb_config Version v25.01-0-g812e032 ==
+VRB1 PF [0000:f7:00.0] configuration complete!
+Log file = /var/log/pf_bb_cfg_0000:f7:00.0.log
+```
+
+#### Creating VFs
+
+Finally, we create the VF(s) for our accelerator. 
+In this example, we only create one SR-IOV VF.
+```
+# echo 1 | sudo tee /sys/bus/pci/devices/0000:f7:00.0/sriov_numvfs
+```
+
+If you encounter any error when creating the VF(s), e.g., `tee: '/sys/bus/pci/devices/0000:f7:00.0/sriov_numvfs': No such file or directory`, then try enabling SR-IOV again.
+```
+# echo 1 | sudo tee /sys/module/vfio_pci/parameters/enable_sriov
+```
+
+After you have successfully created the VF, you should see an additional baseband device, in our case, it is `0000:f7:00.1`. 
+We will use this device with OAI later.
+The newly created VF should also be using the same `vfio-pci` driver as the PF, if it is not, you will need to do a `dpdk-devbind.py` to bind it with `vfio-pci`. 
+```
+# sudo dpdk-devbind.py -s
+...
+Baseband devices using DPDK-compatible driver
+=============================================
+0000:f7:00.0 'Device 57c0' drv=vfio-pci unused=
+0000:f7:00.1 'Device 57c0' drv=vfio-pci unused=
+...
+```
+
+# Building OAI with ORAN-AAL
+OTA deployment is precisely described in the following tutorial:
+- [NR_SA_Tutorial_COTS_UE](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/NR_SA_Tutorial_COTS_UE.md)
+Instead of section *3.2 Build OAI gNB* from the tutorial, run the following commands:
+
+```bash
+# Get openairinterface5g source code
+git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git ~/openairinterface5g
+cd ~/openairinterface5g
+git checkout develop
+
+# Install OAI dependencies
+cd ~/openairinterface5g/cmake_targets
+./build_oai -I
+
+# Build OAI gNB
+cd ~/openairinterface5g
+source oaienv
+cd cmake_targets
+./build_oai -w USRP --ninja --gNB -P --build-lib "ldpc_aal" -C
+```
+
+A shared object file `libldpc_aal.so` will be created during the compilation.
+This object is conditionally compiled. 
+The selection of the library to compile is done using `--build-lib ldpc_aal`.
+
+> Note: The required DPDK poll mode driver has to be present on the host machine and required DPDK version has to be installed on the host, prior to building OAI.
+
+# O-RAN AAL DPDK EAL parameters
+To configure O-RAN AAL/DPDK BBDEV, you can set the following parameters via the command line of PHY simulators or nr-softmodem:
+
+> Note: the group parameter name has been renamed from `nrLDPC_coding_t2` to
+> `nrLDPC_coding_aal` to better reflect that it is a generic AAL accelerator
+> card.
+
+- `nrLDPC_coding_aal.dpdk_dev` - **mandatory** parameter, specifies the PCI address of our accelerator. It must follow the format `WWWW:XX:YY.Z`.
+
+- `nrLDPC_coding_aal.dpdk_core_list` - **mandatory** parameter, specifies the CPU cores assigned to DPDK . 
+Ensure that the CPU cores specified in `nrLDPC_coding_aal.dpdk_core_list` are available and not used by other processes to avoid conflicts.
+
+- `nrLDPC_coding_aal.dpdk_prefix` - optional parameter, DPDK shared data file prefix, by default set to *b6*.
+
+- `nrLDPC_coding_aal.vfio_vf_token` - optional parameter, VFIO token set for the VF, if applicable.
+
+- `nrLDPC_coding_aal.num_harq_codeblock` - optional parameter, size of the HARQ buffer in terms of the number of 32kB blocks, by default set to *512* (maximum for the T2; as for the ACCs, this can be further increased).
+
+- `nrLDPC_coding_aal.is_t2` - optional parameter, set this to 1 when using the Xilinx T2 card.
+
+**Note:** These parameters can also be provided in a configuration file.
+Example for the ACC200:
+```
+nrLDPC_coding_aal : {
+  dpdk_dev : "0000:f7:00.1";
+  dpdk_core_list : "14-15";
+  vfio_vf_token: "00112233-4455-6677-8899-aabbccddeeff";
+};
+
+loader : {
+  ldpc : {
+    shlibversion : "_aal";
+  };
+};
+```
+
+# Running OAI with O-RAN AAL
+
+In general, to offload of the channel coding to the LDPC accelerator, we use use the `--loader.ldpc.shlibversion _aal` option.
+Reminder, if you are using the Xilinx T2 card, make sure to set `--nrLDPC_coding_aal.is_t2 1`.
+
+## 5G PHY simulators
+
+### nr_ulsim
+
+Example command:
+```bash
+cd ~/openairinterface5g
+source oaienv
+cd cmake_targets/ran_build/build
+sudo ./nr_ulsim -n100 -s20 -m20 -r273 -R273 --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 0-1 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
+```
+### nr_dlsim
+
+Example command:
+```bash
+cd ~/openairinterface5g
+source oaienv
+cd cmake_targets/ran_build/build
+sudo ./nr_dlsim -n300 -s30 -R 106 -e 27 --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 0-1 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
+```
+
+## OTA test
+
+### Running OAI gNB with USRP B210/ FHI72
+
+Example command:
+```bash
+cd ~/openairinterface5g
+source oaienv
+cd cmake_targets/ran_build/build
+sudo ./nr-softmodem -O ~/gnb.conf --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 14-15 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
+```
+
+# Known Issue(s)
+
+## BBDEV CPU Usage
+
+When running the E2E setup (this applies to both USRP and FHI72), BBDEV may not be using the list of CPU cores as specified by `nrLDPC_coding_aal.dpdk_core_list` accordingly.
+This is an issue under investigation, and subject for future fixes.
+In the meantime, we recommend allocating idle, and isolated CPU cores in the configuration for BBDEV.
+
+## Potential Low Throughput
+
+The current implementation has been tested to work in an end-to-end setup and is functional. 
+However, there are still opportunities for optimization, particularly in LDPC decoding performance, which is an area of ongoing improvement. 
+As such, downlink/uplink throughput may be suboptimal with the default configurations, but enhancements are actively being explored.
+
+To achieve better E2E performance with the current implementation, we recommend the following adjustments:
+1. Increasing the number of LDPC decoding iterations of the L1, e.g., `max_ldpc_iterations` to 200.
+2. Increasing the BLER targets of the MAC scheduler. 
+
+Example configuration snippet:
+```
+...
+MACRLCs = (
+{
+  num_cc                      = 1;
+  tr_s_preference             = "local_L1";
+  tr_n_preference             = "local_RRC";
+  pusch_TargetSNRx10          = 180;
+  pucch_TargetSNRx10          = 220;
+  dl_bler_target_upper        = .35;
+  dl_bler_target_lower        = .15;
+  ul_bler_target_upper        = .35;
+  ul_bler_target_lower        = .15;
+  pusch_FailureThres          = 1000;
+  ul_max_mcs                  = 28;
+
+}
+);
+
+L1s = (
+{
+  num_cc = 1;
+  tr_n_preference       = "local_mac";
+  prach_dtx_threshold   = 120;
+  pucch0_dtx_threshold  = 100;
+  ofdm_offset_divisor   = 8; #set this to UINT_MAX for offset 0
+  max_ldpc_iterations = 200;
+}
+);
+...
+```

doc/LDPC_T2_OFFLOAD_SETUP.md

@@ -1,158 +0,0 @@
-<table style="border-collapse: collapse; border: none;">
-  <tr style="border-collapse: collapse; border: none;">
-    <td style="border-collapse: collapse; border: none;">
-      <a href="http://www.openairinterface.org/">
-         <img src="./images/oai_final_logo.png" alt="" border=3 height=50 width=150>
-         </img>
-      </a>
-    </td>
-    <td style="border-collapse: collapse; border: none; vertical-align: center;">
-      <b><font size = "5">OAI T1/T2 LDPC offload</font></b>
-    </td>
-  </tr>
-</table>
-
-**Table of Contents**
-
-[[_TOC_]]
-
-This documentation aims to provide a tutorial for AMD Xilinx T2 Telco card integration into OAI and its usage.
-
-# Requirements
-
- - bitstream image and PMD driver for the T2 card provided by AccelerComm
- - DPDK 20.11.9 with patch from Accelercomm: version ACCL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch
- - tested on RHEL7.9, RHEL9.2, Ubuntu 22.04
-
-# DPDK setup
-## DPDK installation
-*Note: Following instructions are valid for ACCL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch version, which is compatible with DPDK 20.11.9. Installation steps, which should be followed for older versions of the patch file (for example ACL_BBDEV_DPDK20.11.3_BL_1006_build_1105_dev_branch_MCT_optimisations_1106_physical_std.patch) are present in older version of this documentation, under the tag 2023.w48.*
-
-```
-# Get DPDK source code
-git clone https://github.com/DPDK/dpdk-stable.git ~/dpdk-stable
-cd ~/dpdk-stable
-git checkout v20.11.9
-git apply ~/ACL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch
-```
-Replace `~/ACL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch` by patch file provided by
-Accelercomm.
-```
-cd ~/dpdk-stable
-meson setup build
-# meson setup --prefix=/opt/dpdk-t2 build for installation with non-default installation prefix
-cd build
-ninja
-sudo ninja install
-sudo ldconfig
-```
-## DPDK configuration
- - load required kernel module
-```
-sudo modprobe vfio-pci
-```
- - check presence of the card and its PCI addres on the host machine
-```
-lspci | grep "Xilinx"
-```
- - bind the card with vfio-pci driver
-```
-sudo python3 ~/dpdk-stable/usertools/dpdk-devbind.py --bind=vfio-pci 41:00.0
-```
-Replace PCI address of the card *41:00.0* by address detected by *lspci | grep "Xilinx"* command
- - hugepages setup (10 x 1GB hugepages)
-```
-sudo python3 ~/dpdk-stable/usertools/dpdk-hugepages.py -p 1G --setup 10G
-```
-
-*Note: device binding and hugepages setup has to be done after every reboot of
-the host machine*
-
-# Modifications in the OAI code
-## DPDK lib and PMD path specification
-If DPDK library was installed into custom path, you have to point to the right directory with `PKG_CONFIG_PATH`, prior to the OAI build. Sample command to set the DPDK path to `/opt/dpdk-t2/lib64/pkgconfig/`:
-```
-export PKG_CONFIG_PATH=/opt/dpdk-t2/lib64/pkgconfig/:$PKG_CONFIG_PATH
-```
-
-# OAI Build
-OTA deployment is precisely described in the following tutorial:
-- [NR_SA_Tutorial_COTS_UE](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/NR_SA_Tutorial_COTS_UE.md)
-Instead of section *3.2 Build OAI gNB* from the tutorial, run following commands:
-
-```
-# Get openairinterface5g source code
-git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git ~/openairinterface5g
-cd ~/openairinterface5g
-git checkout develop
-
-# Install OAI dependencies
-cd ~/openairinterface5g/cmake_targets
-./build_oai -I
-
-# Build OAI gNB
-cd ~/openairinterface5g
-source oaienv
-cd cmake_targets
-./build_oai -w USRP --ninja --gNB -P --build-lib "ldpc_t2" -C
-```
-
-Shared object file *libldpc_t2.so* is created during the compilation. This object is conditionally compiled. Selection of the library to compile is done using *--build-lib ldpc_t2*.
-
-*Required poll mode driver has to be present on the host machine and required DPDK version has to be installed on the host, prior to the build of OAI*
-
-# Setup of T2-related DPDK EAL parameters
-To configure T2-related DPDK Environment Abstraction Layer (EAL) parameters, you can set the following parameters via the command line of PHY simulators or softmodem:
-- `nrLDPC_coding_t2.dpdk_dev` - **mandatory** parameter, specifies PCI address of the T2 card. PCI address of the T2 card can be detected by `lspci | grep "Xilinx"` command.
-- `nrLDPC_coding_t2.dpdk_core_list` - **mandatory** parameter, specifies CPU cores assigned to DPDK for T2 processing. Ensure that the CPU cores specified in *nrLDPC_coding_t2.dpdk_core_list* are available and not used by other processes to avoid conflicts.
-- `nrLDPC_coding_t2.dpdk_prefix` - DPDK shared data file prefix, by default set to *b6*.
-
-**Note:** These parameters can also be provided in a configuration file:
-```
-nrLDPC_coding_t2 : {
-  dpdk_dev : "41:00.0";
-  dpdk_core_list : "14-15";
-};
-
-loader : {
-  ldpc : {
-    shlibversion : "_t2";
-  };
-};
-```
-
-# 5G PHY simulators
-
-## nr_ulsim test
-Offload of the channel decoding to the T2 card is in nr_ulsim specified by *--loader.ldpc.shlibversion _t2* option. Example command for running nr_ulsim with LDPC decoding offload to the T2 card:
-```
-cd ~/openairinterface5g
-source oaienv
-cd cmake_targets/ran_build/build
-sudo ./nr_ulsim -n100 -s20 -m20 -r273 -R273 --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
-```
-## nr_dlsim test
-Offload of the channel encoding to the AMD Xilinx T2 card is in nr_dlsim specified by *-c* option. Example command for running nr_dlsim with LDPC encoding offload to the T2 card:
-```
-cd ~/openairinterface5g
-source oaienv
-cd cmake_targets/ran_build/build
-sudo ./nr_dlsim -n300 -s30 -R 106 -e 27 --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
-```
-
-# OTA test
-Offload of the channel encoding and decoding to the AMD Xilinx T2 card is enabled by *--loader.ldpc.shlibversion _t2* option.
-
-## Run OAI gNB with USRP B210
-```
-cd ~/openairinterface5g
-source oaienv
-cd cmake_targets/ran_build/build
-sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
-```
-
-# Limitations
-## AMD Xilinx T2 card
- - functionality of the LDPC encoding and decoding offload verified in OTA SISO setup with USRP N310 and Quectel RM500Q, blocking of the card reported for MIMO setup (2 layers)
-
-*Note: AMD Xilinx T1 Telco card is not supported anymore.*

doc/README.md

@@ -64,7 +64,7 @@ There is some general information in the [OpenAirInterface Gitlab Wiki](https://
 - [How to run with E2 agent](../openair2/E2AP/README.md)
 - [How to run the physical simulators](./physical-simulators.md)
 - [How to setup OAI with Nvidia Aerial and Foxconn](./Aerial_FAPI_Split_Tutorial.md)
-- [How to setup OAI with AMD T2 Telco card](./LDPC_T2_OFFLOAD_SETUP.md)
+- [How to setup OAI with LDPC accelerators (Xilinx T2/Intel ACCs)](./LDPC_OFFLOAD_SETUP.md)
 - [How to do a handover](./handover-tutorial.md)
 - [How to setup gNB frequency](./gNB_frequency_setup.md)
 

openair1/PHY/CODING/DOC/LDPCImplementation.md

@@ -28,35 +28,35 @@ shlib_path libldpc.so
 `libldpc.so` has its decoder implemented in [nrLDPC_coding_segment_decoder.c](file://../nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_decoder.c).\
 Its encoder is implemented in [nrLDPC_coding_segment_encoder.c](file://../nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c).
 
-loading `libldpc_t2.so` instead of `libldpc.so`:
+loading `libldpc_aal.so` instead of `libldpc.so`:
 
-`make ldpc_t2`
+`make ldpc_aal`
 
-This command creates the `libldpc_t2.so` shared library.
+This command creates the `libldpc_aal.so` shared library.
 
 ```
-Building C object CMakeFiles/ldpc_t2.dir/openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_t2/nrLDPC_coding_t2.c.o
-Linking C shared module libldpc_t2.so
+Building C object CMakeFiles/ldpc_aal.dir/openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/nrLDPC_coding_aal.c.o
+Linking C shared module libldpc_aal.so
 ```
 
-At runtime, to successfully use the T2 board, you need to install vendor specific drivers and tools.\
-Please refer to the dedicated documentation at [LDPC_T2_OFFLOAD_SETUP.md](file://../../../../doc/LDPC_T2_OFFLOAD_SETUP.md).
+At runtime, to successfully use LDPC accelerators (e.g., Xilinx T2/Intel ACCs), you will need to install the corresponding drivers and tools.
+Please refer to the dedicated documentation at [LDPC_OFFLOAD_SETUP.md](file://../../../../doc/LDPC_OFFLOAD_SETUP.md).
 
-`./nr-softmodem -O  libconfig:gnb.band78.sa.fr1.106PRB.usrpb210.conf:dbgl5 --rfsim --rfsimulator.serveraddr server  --log_config.gtpu_log_level info  --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1`
+`./nr-softmodem -O  libconfig:gnb.band78.sa.fr1.106PRB.usrpb210.conf:dbgl5 --rfsim --rfsimulator.serveraddr server  --log_config.gtpu_log_level info  --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 01:00.0 --nrLDPC_coding_aal.dpdk_core_list 0-1`
 
 ``` 
 
 .......................
 [CONFIG] loader.ldpc.shlibversion set to default value ""
 [LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value)
-[CONFIG] shlibversion set to  _t2 from command line
+[CONFIG] shlibversion set to  _aal from command line
 [CONFIG] loader.ldpc 1 options set from command line
-shlib_path libldpc_t2.so
-[LOADER] library libldpc_t2.so successfully loaded
+shlib_path libldpc_aal.so
+[LOADER] library libldpc_aal.so successfully loaded
 ........................
 ```
 
-`libldpc_t2.so` has its decoder and its encoder implemented in [nrLDPC_coding_t2.c](file://../nrLDPC_coding/nrLDPC_coding_t2/nrLDPC_coding_t2.c).
+`libldpc_aal.so` has its decoder and its encoder implemented in [nrLDPC_coding_aal.c](file://../nrLDPC_coding/nrLDPC_coding_aal/nrLDPC_coding_aal.c).
 
 loading `libldpc_xdma.so` instead of `libldpc.so`:
 
@@ -103,7 +103,7 @@ Libraries implementing the slotwise LDPC coding must be named `libldpc<_version>
 
 `libldpc.so` is completed.
 
-`libldpc_t2.so` is completed.
+`libldpc_aal.so` is completed.
 
 `libldpc_xdma.so` is completed.
 

openair1/PHY/CODING/nrLDPC_coding/CMakeLists.txt

@@ -1,3 +1,3 @@
 add_subdirectory(nrLDPC_coding_segment)
 add_subdirectory(nrLDPC_coding_xdma)
-add_subdirectory(nrLDPC_coding_t2)
+add_subdirectory(nrLDPC_coding_aal)

openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/CMakeLists.txt

@@ -0,0 +1,36 @@
+##########################################################
+# LDPC offload library - O-RAN AAL/DPDK BBDEV
+##########################################################
+
+add_boolean_option(ENABLE_LDPC_AAL OFF "Build support for LDPC Offload using O-RAN AAL library" OFF)
+
+if (ENABLE_LDPC_AAL)
+  pkg_check_modules(LIBDPDK_AAL REQUIRED libdpdk>=20.11.9)
+
+  find_library(PMD_T2 NAMES rte_baseband_accl_ldpc HINTS ${LIBDPDK_AAL_LIBRARY_DIRS})
+  if (PMD_T2)
+    message(STATUS "found poll-mode driver for AccelerComm T2 LDPC Offload (rte_baseband_accl_ldpc.so)")
+  else()
+    if (LIBDPDK_AAL_VERSION VERSION_LESS "22.11")
+      message(FATAL_ERROR "for non-T2 BBDEV PMDs, we support the Intel ACC100 and ACC200 (VRB1), using DPDK 22.11 or later.")
+    endif()
+  endif()
+
+  add_library(ldpc_aal MODULE nrLDPC_coding_aal.c)
+
+  set_target_properties(ldpc_aal PROPERTIES COMPILE_FLAGS "-DALLOW_EXPERIMENTAL_API")
+  set_target_properties(ldpc_aal PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
+  target_include_directories(ldpc_aal PRIVATE ${LIBDPDK_AAL_INCLUDE_DIRS})
+  target_link_libraries(ldpc_aal PRIVATE ldpc_gen_HEADERS ${LIBDPDK_AAL_LDFLAGS})
+  if (PMD_T2)
+    target_link_libraries(ldpc_aal PRIVATE ${PMD_T2})
+  endif()
+
+  add_dependencies(nr-softmodem ldpc_aal)
+  add_dependencies(nr-uesoftmodem ldpc_aal)
+  add_dependencies(nr_ulsim ldpc_aal)
+  add_dependencies(nr_ulschsim ldpc_aal)
+  add_dependencies(nr_dlsim ldpc_aal)
+  add_dependencies(nr_dlschsim ldpc_aal)
+
+endif()

openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/README.md

@@ -0,0 +1,143 @@
+This document highlights some of the key aspects of the implementation for O-RAN AAL/DPDK BBDEV; for user documentation, please consult the [setup guide](../../../../../doc/LDPC_OFFLOAD_SETUP.md) instead.
+
+## Overview
+
+The current implementation supports the following BBDEV devices and respective DPDK versions:
+- Xilinx T2 on DPDK20.11+
+- Intel ACC100* on DPDK22.11+
+- Intel ACC200 (VRB1) on DPDK22.11+
+
+> Important notes: 
+> - For the Intel ACC100, for DPDK22.11 and DPDK23.11, users are required to [patch](https://github.com/DPDK/dpdk/commit/fdde63a1dfc129d0a510a831aa98253b36a2a1cd) the ACC100's driver.
+> - If you intend to use this implementation in an FHI7.2 setup, only the F-release and beyond is supported.
+
+## Implementation Details
+
+Below, we highlight some of the important details in this implementation.
+
+### HARQ 
+
+To maintain the HARQ buffers in the LDPC decoding process, the BBDEV either uses its internal memory (not visible to DPDK), or using external memory (i.e., DDR) managed by OAI. 
+For the Xilinx T2 and Intel ACC100, they use the internal memory while the Intel ACC200 uses the DDR memory.
+
+If internal memory is supported by the device, we will set `RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE` and `RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`.
+
+The following two fields are important for HARQ: `harq_combined_input` and `harq_combined_output`.
+
+For the first transmission, there is no HARQ input.
+Thus, the flag `RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE` is not set.
+However, there will be a HARQ output, so we set the flag `RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`.
+We also set the corresponding fields for `harq_combined_output`.
+
+For the second transmission (or subsequent retransmissions), we need to provide a HARQ input at the same time, there will also be a HARQ output.
+Therefore, both fields, `harq_combined_input` and `harq_combined_output` must be set accordingly.
+
+As HARQ requires the output of the previous transmission/ HARQ round as its input, we need to maintain a separate variable to hold the previous round's information. 
+To do so, we define `harq_buffers` (which is a pointer to an array of size `num_harq_codeblock` allocated in the heap later) in the `active_device` struct (see the following) in our implementation.
+```C
+struct active_device {
+  ...
+  uint32_t num_harq_codeblock;
+  /* Persistent data structure to keep track of HARQ-related information */
+  // Note: This is used to store/keep track of the combined output information across iterations
+  struct rte_bbdev_op_data *harq_buffers;
+  ...
+} active_dev;
+```
+
+
+In the following, we elaborate on how the HARQ-related fields are set.
+
+#### Internal Memory
+
+When using the internal memory, we need to specify the *offset* of the hardware's memory where we want to store the HARQ combined output, and read from it accordingly later.
+
+In the current implementation, we use a fixed offset of 32K, i.e., this means that each block is 32K. 
+
+An index is derived from a unique HARQ PID assigned by OAI, modulo `active_dev.num_harq_codeblock` (which is configurable by the user through `nrLDPC_coding_t2.num_harq_codeblock`).
+Using that index, we then derived the corresponding offset in the memory (i.e., `harq_combined_offset`).
+
+```C
+...
+
+// Calculate offset in the HARQ combined buffers
+// Unique segment offset
+uint32_t segment_offset = (nrLDPC_slot_decoding_parameters->TBs[h].harq_unique_pid * NR_LDPC_MAX_NUM_CB) + i;
+// Prune to avoid shooting above maximum id
+uint32_t pruned_segment_offset = segment_offset % active_dev.num_harq_codeblock;
+// Segment offset to byte offset
+uint32_t harq_combined_offset = pruned_segment_offset * LDPC_MAX_CB_SIZE;
+
+...
+```
+
+This `harq_combined_offset` is then set for `harq_combined_input.offset` and `harq_combined_output.offset` to tell BBDEV where to read/write the HARQ buffers.
+
+Especially for the Intel ACCs, when providing the HARQ input, the `harq_combined_input.length` must be provided. 
+To do so, we maintain the length of previous round's output using `harq_buffers` by copying it in `retrieve_ldpc_dec_op`.
+
+#### External Memory
+
+Different from the Xilinx T2 and Intel ACC100, the Intel ACC200 uses DDR memory to maintain the HARQ buffers which is managed by OAI.
+
+In short, we use `harq_buffers` from the `active_device` struct, which have been initialzed with corresponding DPDK mempools for BBDEV to read/write the HARQ input/outputs.
+
+For indexing, we use the `pruned_segment_offset`, which is derived from the unique HARQ PID assigned by OAI, modulo `active_dev.num_harq_codeblock` (which is configurable by the user through `nrLDPC_coding_t2.num_harq_codeblock`).
+
+`harq_combined_input.offset` and `harq_combined_output.offset` is always set to 0 in our implementation.
+Instead, we provide BBDEV the pointers to our allocated mempool regions through `harq_combined_input.data` and `harq_combined_output.data`.
+
+In `retrieve_ldpc_dec_op`, we perform a `rte_memcpy` to copy the HARQ combined outputs to `harq_buffers`, along with other necessary metadata information to prepare for subsequent HARQ rounds.
+Similar to the Intel ACC100, when providing the HARQ input, the `harq_combined_input.length` must be provided. 
+
+### LLR Scaling
+
+The LLR output from OAI's demodulation block is in 16 bits.
+However, accelerators typically assume that the LLR inputs are scaled down using fixed-point arithmetic, e.g., 8 bits.
+
+For the Xilinx T2, saturation is performed.
+However, our tests have shown that this implementation did not work well for the Intel ACCs.
+
+To that end, we perform LLR scaling differently for the Intel ACCs.
+Through the function `llr_scaling`, we look at the min and max LLR values, perform scaling and subsequently saturation accordingly.
+
+The fixed-point representations supported by the hardware is defined by the `llr_size` and `llr_decimal`.
+For example, if `llr_size=8`, and `llr_decimal=1`, it means that we use a S8.1 representation (1 fractional bit), the min and max values are -64 to 63.5.
+
+> *Limitation:* 
+> We observe that in certain configurations, such as when using 2 MIMO layers, the LLR (Log-Likelihood Ratio) outputs exhibit a much wider dynamic range (e.g., from -10,000 to 10,000) compared to the typical sub-1,000 range seen in most other cases. 
+> This suggests potential inconsistencies in the LLR values generated by the demodulator. 
+> We believe that the decoding performance, when compared to the CPU implementation under the same number of LDPC decoding iterations, could be improved by refining the LLR scaling approach or revisiting the LLR generation process during demodulation. 
+> This remains an area of active investigation.
+>
+> *Workaround:*
+> As a temporary measure, increasing the number of LDPC decoding iterations—e.g., to 150—has shown to yield a decoding success rate comparable to that of the CPU implementation. 
+> This comes at a negligible increase in decoding time based on our current evaluation.
+
+### Special Case(s)
+
+#### TB mode
+
+For the T2, only CB mode is supported.
+
+For the Intel ACCs, while we also use CB mode mostly, there is a special case that must be handled properly as specified by the BBDEV documentations: 
+```
+... The case when one CB belongs to TB and is being enqueued individually to BBDEV, this case is considered as a special case of partial TB where its number of CBs is 1. Therefore, it requires to get processed in TB-mode. ...
+```
+
+In such a case, we perform a check on whether there is only one TB, AND if the TB has only one CB.
+If so, this has to be handled separately by using TB mode.
+
+### Future Work(s)
+
+#### TB mode
+
+The current channel coding interface assumes LDPC encoding and decoding are performed on a per-code block basis.
+However, to fully leverage Transport Block (TB) mode as supported in BBDEV, which can improve efficiency, the L1 implementation surrounding channel coding needs to be refactored. 
+This remains an area for future investigation.
+
+#### CRC24A/CRC16
+
+CRC24A/CRC16 is supported by the BBDEV device (i.e., Intel ACC200). 
+However, we do not make use of them and rely on OAI's existing CRC functions.
+To use of BBDEV's CRC24A/CRC16 capability will be looked into in future MRs.

openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/nrLDPC_coding_aal.h

@@ -2,8 +2,8 @@
  * Copyright(c) 2017 Intel Corporation
  */
 
-#ifndef _MAIN_H_
-#define _MAIN_H_
+#ifndef __NRLDPC_CODING_T2_H__
+#define __NRLDPC_CODING_T2_H__
 
 #include <stddef.h>
 #include <sys/queue.h>
@@ -17,6 +17,7 @@
 enum op_data_type {
   DATA_INPUT = 0,
   DATA_HARD_OUTPUT,
+  DATA_HARQ_OUTPUT,
   DATA_NUM_TYPES,
 };
 

openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_t2/CMakeLists.txt

@@ -1,31 +0,0 @@
-##########################################################
-
-# LDPC offload library - AMD T2 Accelerator Card
-##########################################################
-
-add_boolean_option(ENABLE_LDPC_T2 OFF "Build support for LDPC Offload to T2 library" OFF)
-
-if (ENABLE_LDPC_T2)
-
-  pkg_check_modules(LIBDPDK_T2 REQUIRED libdpdk>=20.11.9)
-
-  find_library(PMD_T2 NAMES rte_baseband_accl_ldpc HINTS ${LIBDPDK_T2_LIBRARY_DIRS})
-  if (NOT PMD_T2)
-    message(FATAL_ERROR "could not find poll-mode driver for AccelerComm T2 LDPC Offload (rte_baseband_accl_ldpc.so)")
-  endif()
-
-  message(STATUS "T2 build: use ${PMD_T2}")
-  add_library(ldpc_t2 MODULE nrLDPC_coding_t2.c)
-
-  set_target_properties(ldpc_t2 PROPERTIES COMPILE_FLAGS "-DALLOW_EXPERIMENTAL_API")
-  set_target_properties(ldpc_t2 PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
-  target_link_libraries(ldpc_t2 PRIVATE ldpc_gen_HEADERS ${LIBDPDK_T2_LDFLAGS} ${PMD_T2})
-
-  add_dependencies(nr-softmodem ldpc_t2)
-  add_dependencies(nr-uesoftmodem ldpc_t2)
-  add_dependencies(nr_ulsim ldpc_t2)
-  add_dependencies(nr_ulschsim ldpc_t2)
-  add_dependencies(nr_dlsim ldpc_t2)
-  add_dependencies(nr_dlschsim ldpc_t2)
-
-endif()

radio/fhi_72/oran-config.c

@@ -485,19 +485,19 @@ static bool set_fh_io_cfg(struct xran_io_cfg *io_cfg, const paramdef_t *fhip, in
   char *shlibversion = NULL; // version of the LDPC coding library
   paramdef_t LoaderParams_shlibversion[] = {{"shlibversion", NULL, 0, .strptr = &shlibversion, .defstrval = NULL, TYPE_STRING, 0, NULL}};
   config_get(config_get_if(), LoaderParams_shlibversion, sizeofArray(LoaderParams_shlibversion), "loader.ldpc");
-  if (shlibversion != NULL && strncmp(shlibversion, "_t2", 3) == 0) {
-    uint32_t eal_init_bbdev = 0;    // If not 0 then include the BBDEV device in the EAL init for FHI
+  if (shlibversion != NULL && strncmp(shlibversion, "_aal", 4) == 0) {
+    uint32_t is_t2 = 0;    // If not 0 then include the BBDEV device in the EAL init for FHI
     char *dpdk_dev = NULL;          // PCI address of the card
     char *vfio_vf_token = NULL;     // vfio token for the bbdev card
     paramdef_t LoaderParams[] = {
-      {"eal_init_bbdev", NULL, 0, .uptr = &eal_init_bbdev, .defuintval = 0, TYPE_UINT, 0, NULL},
+      {"is_t2", NULL, 0, .uptr = &is_t2, .defuintval = 0, TYPE_UINT, 0, NULL},
       {"dpdk_dev", NULL, 0, .strptr = &dpdk_dev, .defstrval = NULL, TYPE_STRING, 0, NULL},
       {"vfio_vf_token", NULL, 0, .strptr = &vfio_vf_token, .defstrval = NULL, TYPE_STRING, 0, NULL}
     };
-    config_get(config_get_if(), LoaderParams, sizeofArray(LoaderParams), "nrLDPC_coding_t2");
+    config_get(config_get_if(), LoaderParams, sizeofArray(LoaderParams), "nrLDPC_coding_aal");
 
-    if (eal_init_bbdev != 0) {
-      AssertFatal(dpdk_dev!=NULL, "nrLDPC_coding_t2.dpdk_dev was not provided");
+    if (!is_t2) {
+      AssertFatal(dpdk_dev!=NULL, "nrLDPC_coding_aal.dpdk_dev was not provided");
       snprintf(&bbdev_dev[0], sizeof(bbdev_dev), "%s", dpdk_dev);
       io_cfg->bbdev_dev[0] = &bbdev_dev[0]; // BBDev dev name; max devices = 1
       if(vfio_vf_token != NULL) {

radio/vrtsim/vrtsim.c

@@ -48,12 +48,13 @@
 #include "simde/x86/avx512.h"
 
 // Simulator role
-typedef enum { ROLE_SERVER = 1, ROLE_CLIENT } role;
+typedef enum { ROLE_SERVER = 1, ROLE_CLIENT, ROLE_EMULATOR } role;
 
 #define NUM_CHANMOD_THREADS 1
 
 #define ROLE_CLIENT_STRING "client"
 #define ROLE_SERVER_STRING "server"
+#define ROLE_EMULATOR_STRING "emulator"
 
 #define VRTSIM_SECTION "vrtsim"
 #define TIME_SCALE_HLP \
@@ -62,10 +63,10 @@ typedef enum { ROLE_SERVER = 1, ROLE_CLIENT } role;
 // clang-format off
 #define VRTSIM_PARAMS_DESC \
   { \
-     {"channel_name", "shared memory channel name\n",  0, .strptr = &channel_name,               .defstrval = "vrtsim_channel", TYPE_STRING, 0}, \
-     {"role",         "either client or server\n",     0, .strptr = &role,                       .defstrval = ROLE_CLIENT_STRING,  TYPE_STRING, 0}, \
-     {"timescale",    TIME_SCALE_HLP,                  0, .dblptr = &vrtsim_state->timescale, .defdblval = 1.0,                 TYPE_DOUBLE, 0}, \
-     {"chanmod",      "Enable channel modelling",      0, .iptr = &vrtsim_state->chanmod,     .defintval = 0,                   TYPE_INT,    0}, \
+     {"channel_name", "shared memory channel name\n",        0, .strptr = &channel_name,            .defstrval = "vrtsim_channel",    TYPE_STRING, 0}, \
+     {"role",         "either client, server or emulator\n", 0, .strptr = &role,                    .defstrval = ROLE_CLIENT_STRING,  TYPE_STRING, 0}, \
+     {"timescale",    TIME_SCALE_HLP,                        0, .dblptr = &vrtsim_state->timescale, .defdblval = 1.0,                 TYPE_DOUBLE, 0}, \
+     {"chanmod",      "Enable channel modelling",            0, .iptr = &vrtsim_state->chanmod,     .defintval = 0,                   TYPE_INT,    0}, \
   };
 // clang-format on
 
@@ -165,6 +166,8 @@ static void vrtsim_readconfig(vrtsim_state_t *vrtsim_state)
     vrtsim_state->role = ROLE_CLIENT;
   } else if (strncmp(role, ROLE_SERVER_STRING, strlen(ROLE_SERVER_STRING)) == 0) {
     vrtsim_state->role = ROLE_SERVER;
+  } else if (strncmp(role, ROLE_EMULATOR_STRING, strlen(ROLE_EMULATOR_STRING)) == 0) {
+    vrtsim_state->role = ROLE_EMULATOR;
   } else {
     AssertFatal(false, "Invalid role configuration\n");
   }
@@ -305,8 +308,10 @@ static int vrtsim_connect(openair0_device *device)
   peer_info_t peer_info = {.num_rx_antennas = device->openair0_cfg[0].rx_num_channels};
   if (vrtsim_state->role == ROLE_SERVER) {
     vrtsim_state->peer_info = server_exchange_peer_info(peer_info);
-  } else {
+  } else if (vrtsim_state->role == ROLE_CLIENT) {
     vrtsim_state->peer_info = client_exchange_peer_info(peer_info);
+  } else if (vrtsim_state->role == ROLE_EMULATOR) {
+    vrtsim_state->peer_info = peer_info;
   }
 
   // Handle channel modelling after number of RX antennas are known
@@ -338,8 +343,16 @@ static int vrtsim_connect(openair0_device *device)
     }
     int ret = pthread_create(&vrtsim_state->timing_thread, NULL, vrtsim_timing_job, vrtsim_state);
     AssertFatal(ret == 0, "pthread_create() failed: errno: %d, %s\n", errno, strerror(errno));
-  } else {
+  } else if (vrtsim_state->role == ROLE_CLIENT) {
     vrtsim_state->channel = shm_td_iq_channel_connect(vrtsim_state->channel_name, 10);
+  } else {
+    vrtsim_state->channel = shm_td_iq_channel_emulator_create(vrtsim_state->channel_name,
+                                                              vrtsim_state->peer_info.num_rx_antennas,
+                                                              device->openair0_cfg[0].rx_num_channels);
+    vrtsim_state->run_timing_thread = true;
+    shm_td_iq_channel_emulator_connect(vrtsim_state->channel);
+    int ret = pthread_create(&vrtsim_state->timing_thread, NULL, vrtsim_timing_job, vrtsim_state);
+    AssertFatal(ret == 0, "pthread_create() failed: errno: %d, %s\n", errno, strerror(errno));
   }
 
   return 0;
@@ -487,6 +500,40 @@ static int vrtsim_write(openair0_device *device, openair0_timestamp timestamp, v
                                : vrtsim_write_internal(vrtsim_state, timestamp, (c16_t *)samplesVoid[0], nsamps, 0, flags, 0);
 }
 
+static void inject_noise_rx(void **samplesVoid, int nsamps, int nbAnt)
+{
+
+  for (int aarx = 0; aarx < nbAnt; aarx++) {
+    int aligned_nsamps = ceil_mod(nsamps, (512 / 8) / sizeof(cf_t));
+    cf_t samples[aligned_nsamps] __attribute__((aligned(64)));
+    // Apply noise from global settings
+    get_noise_vector((float *)samples, nsamps * 2);
+
+    // Convert to c16_t
+    c16_t samples_out[aligned_nsamps] __attribute__((aligned(64)));
+#if defined(__AVX512F__)
+    for (int i = 0; i < aligned_nsamps / 8; i++) {
+      simde__m512 *in = (simde__m512 *)&samples[i * 8];
+      simde__m256i *out = (simde__m256i *)&samples_out[i * 8];
+      *out = simde_mm512_cvtsepi32_epi16(simde_mm512_cvtps_epi32(*in));
+    }
+#elif defined(__AVX2__)
+    for (int i = 0; i < aligned_nsamps / 4; i++) {
+      simde__m256 *in = (simde__m256 *)&samples[i * 4];
+      simde__m128i *out = (simde__m128i *)&samples_out[i * 4];
+      *out = simde_mm256_cvtsepi32_epi16(simde_mm256_cvtps_epi32(*in));
+    }
+#else
+    for (int i = 0; i < nsamps; i++) {
+      samples_out[i].r = lroundf(samples[i].r);
+      samples_out[i].i = lroundf(samples[i].i);
+    }
+#endif
+    memcpy(samplesVoid[aarx], samples_out, nsamps * sizeof(c16_t));
+  }
+
+}
+
 static int vrtsim_read(openair0_device *device, openair0_timestamp *ptimestamp, void **samplesVoid, int nsamps, int nbAnt)
 {
   vrtsim_state_t *vrtsim_state = (vrtsim_state_t *)device->priv;
@@ -500,13 +547,16 @@ static int vrtsim_read(openair0_device *device, openair0_timestamp *ptimestamp,
   vrtsim_state->rx_samples_total += nsamps;
   *ptimestamp = vrtsim_state->last_received_sample;
   vrtsim_state->last_received_sample += nsamps;
+  if (vrtsim_state->role == ROLE_EMULATOR) {
+    inject_noise_rx(samplesVoid, nsamps, nbAnt);
+  }
   return nsamps;
 }
 
 static void vrtsim_end(openair0_device *device)
 {
   vrtsim_state_t *vrtsim_state = (vrtsim_state_t *)device->priv;
-  if (vrtsim_state->role == ROLE_SERVER) {
+  if (vrtsim_state->role == ROLE_SERVER || vrtsim_state->role == ROLE_EMULATOR) {
     vrtsim_state->run_timing_thread = false;
     int ret = pthread_join(vrtsim_state->timing_thread, NULL);
     AssertFatal(ret == 0, "pthread_join() failed: errno: %d, %s\n", errno, strerror(errno));
@@ -565,9 +615,13 @@ __attribute__((__visibility__("default"))) int device_init(openair0_device *devi
 {
   vrtsim_state_t *vrtsim_state = calloc_or_fail(1, sizeof(vrtsim_state_t));
   vrtsim_readconfig(vrtsim_state);
-  LOG_I(HW,
-        "Running as %s\n",
-        vrtsim_state->role == ROLE_SERVER ? "server: waiting for client to connect" : "client: will connect to a vrtsim server");
+  char *log_role = "server: waiting for client to connect";
+  if (vrtsim_state->role == ROLE_CLIENT) {
+    log_role = "client: will connect to a vrtsim server";
+  } else if (vrtsim_state->role == ROLE_EMULATOR) {
+    log_role = "emulator: will emulate RF";
+  }
+  LOG_I(HW, "Running as %s\n", log_role);
   device->trx_start_func = vrtsim_connect;
   device->trx_reset_stats_func = vrtsim_stub;
   device->trx_end_func = vrtsim_end;