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62 Commits

Author SHA1 Message Date
Robert Schmidt
220d851deb Merge branch 'integration_2024_w44' into 'develop'
Integration: `2024.w44`

See merge request oai/openairinterface5g!3081

* !2988 Add functional DFT test
* !3072 snow3g: fix array size
* !3073 small fix for 3 digit mnc usage in sib1
* !3040 Update pbchsim to work with other numerologies
* !3078 Simplify logs in gNB&UE
* !3080 Add Fedora 41, build_oai cleanup
* !3061 RLC optimization
* !3008 Fix regression 4g
* !3084 Fix a typo in nrue.uicc.yaml file
* !3085 chore(ci): creating a develop tag on top of develop-commit-id tag for the local private registry
2024-11-05 11:58:33 +00:00
Robert Schmidt
e3c3a8a6ff Merge remote-tracking branch 'origin/ci-add-develop-tag-in-private-repo' into integration_2024_w44 (!3085)
chore(ci): creating a develop tag on top of develop-commit-id tag for the local private registry

Create a 2nd tag of develop for all images on the local registry.  We
are doing this in order to simplify cross-repository testing between
FlexRIC and RAN.
2024-11-05 11:03:02 +01:00
Robert Schmidt
70885cc959 Merge remote-tracking branch 'origin/nrue-yaml-hotfix' into integration_2024_w44 (!3084)
Fix two issues with softmodem yaml files

- Fix a typo that prevents casting max_chan to integer in nrue.uicc.yaml
- Remove unused field ssb_PositionsInBurst_PR from gNB example config
  yaml file
2024-11-05 11:02:24 +01:00
Robert Schmidt
f216c47ace Merge remote-tracking branch 'origin/fix-regression-4G' into integration_2024_w44 (!3008)
Fix Regression 4G

- Fix various bugs and/or regressions in 4G code
- Also, the CI does not test RFsim 4G with --sanitize, enables this to
  detect problems.
2024-11-04 19:43:52 +01:00
Robert Schmidt
01aadcac1f Merge remote-tracking branch 'origin/rlc-optimization' into integration_2024_w44 (!3061)
RLC optimization

Two improvements:

- using functions instead of function pointers which enables inlining
- avoid 1 malloc/free per SDU

Benchmark results:

before:

    BM_nr_rlc_am_entity/20000           5036721 ns      5036541 ns          138
    BM_nr_rlc_am_entity/20000           5032061 ns      5031849 ns          138
    BM_nr_rlc_am_entity/20000           5037071 ns      5037056 ns          138
    BM_nr_rlc_am_entity/20000           5035472 ns      5035248 ns          138
    BM_nr_rlc_am_entity/20000           5032860 ns      5032681 ns          138
    BM_nr_rlc_am_entity/20000_mean      5034837 ns      5034675 ns            5
    BM_nr_rlc_am_entity/20000_median    5035472 ns      5035248 ns            5
    BM_nr_rlc_am_entity/20000_stddev       2267 ns         2315 ns            5
    BM_nr_rlc_am_entity/20000_cv           0.05 %          0.05 %             5

after:

    BM_nr_rlc_am_entity/20000           4974403 ns      4974202 ns          140
    BM_nr_rlc_am_entity/20000           4976705 ns      4976444 ns          140
    BM_nr_rlc_am_entity/20000           5004550 ns      5004508 ns          140
    BM_nr_rlc_am_entity/20000           4974652 ns      4974460 ns          140
    BM_nr_rlc_am_entity/20000           4976447 ns      4976225 ns          140
    BM_nr_rlc_am_entity/20000_mean      4981351 ns      4981168 ns            5
    BM_nr_rlc_am_entity/20000_median    4976447 ns      4976225 ns            5
    BM_nr_rlc_am_entity/20000_stddev      13009 ns        13087 ns            5
    BM_nr_rlc_am_entity/20000_cv           0.26 %          0.26 %             5
2024-11-04 19:42:43 +01:00
Raphael Defosseux
5e7fa3fc64 chore(ci): creating a develop tag on top of develop-commit-id tag for the local private registry
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
2024-11-04 15:12:20 +01:00
Bartosz Podrygajlo
63fb3af917 Remove unused ssb_PositionsInBurst_PR field from gNB yaml file example 2024-11-04 14:47:46 +01:00
Bartosz Podrygajlo
7a4aa41c90 Fix a typo in nrue.uicc.yaml file
Fix a typo that prevents casting max_chan to integer
2024-11-04 13:07:56 +01:00
Robert Schmidt
1b1be2ebea Merge remote-tracking branch 'origin/fedora-41-cleanup' into integration_2024_w44 (!3080)
Add Fedora 41, build_oai cleanup

- Add Fedora 41 to list of supported distributions
- Remove some dependencies in RHEL that are not necessary
- Cleanup some build_oai documentation of non-supported options
2024-11-01 11:59:44 +01:00
Robert Schmidt
da7a028a3f Merge remote-tracking branch 'origin/logs-refactor-orange' into integration_2024_w44 (!3078)
Simplify logs in gNB&UE

- reduce the amount of printf() that outputs useless info
- in MAC, PHY, NGAP, RRC, mark some "important" UE events with LOG_A for
  better visibility -> can put log_config.global_log_level analysis to
  only see important stuff
- in RRC, use some macro to consistently print logs
- track the cellID of a UE in RRC
2024-11-01 11:58:47 +01:00
Robert Schmidt
25405d1720 Merge remote-tracking branch 'origin/NR_PBCHSIM_changes' into integration_2024_w44 (!3040)
Update pbchsim to work with other numerologies

NR PBCHSIM updated to work with 15Khz and 120Khz.
2024-11-01 11:58:13 +01:00
Robert Schmidt
9d96326ce7 Remove RHEL8 from list of supported distributions 2024-10-31 12:53:08 +01:00
Robert Schmidt
d6938e7b2a Remove useless options: -x does nothing 2024-10-31 12:53:08 +01:00
Robert Schmidt
8d62bc38c0 Remove documented but unsupported build_oai options 2024-10-31 12:53:08 +01:00
Robert Schmidt
a93ad34c6b Remove non-required dependencies from install list
openssl and libffi are not required for building OAI. Remove them.
2024-10-31 12:53:08 +01:00
Robert Schmidt
9f56b8e21f Add Fedora 41 to list of supported distributions 2024-10-31 12:53:08 +01:00
Robert Schmidt
24e591df59 Merge remote-tracking branch 'origin/3-digit-mnc-in-sib1' into integration_2024_w44 (!3073)
small fix for 3 digit mnc usage in sib1

When 3 digit MNC is used in PLMN, during preparation of SIB1, first
digit of MNC was not taking into account. UE derives Serving Network
Name (SNN) using PLMN info from sib1. Because of 5GCore and UE has
different SNNs, this leads to XRES*, RES* mismatch during Authentication
Procedure between 5GCore and UE. (SNN is used for derivation of these
keys)
2024-10-31 08:41:20 +01:00
Robert Schmidt
571d1fceab Merge remote-tracking branch 'origin/hotfix-snow3g' into integration_2024_w44 (!3072)
snow3g: fix array size
2024-10-31 08:40:57 +01:00
Robert Schmidt
84db6fd9f3 Merge remote-tracking branch 'origin/add-functional-test-dft' into integration_2024_w44 (!2988)
Add functional DFT test

- clean up code on (i)dft calls
- add DFT test for some DFT sizes against trivial implementation: it
  tests a simple square signal in only real values
- correctly scale DFT-16
2024-10-31 08:40:21 +01:00
Robert Schmidt
55feed3645 Add chart for nr_pbchsim.otherSCS execution 2024-10-31 08:26:00 +01:00
Laurent THOMAS
ae8df083fc Add functional test for DFT 2024-10-30 18:04:59 +01:00
Laurent THOMAS
576d468809 Clean up intermediate DFT macros, remove non-existing DFTs
DFT for 9216 and 73728 don't exist and/or assert, so remove them from
the list.
2024-10-30 18:04:43 +01:00
Robert Schmidt
ffa3260ab5 Set explicit wd, set LD_LIBRARY_PATH to find dfts.so 2024-10-30 17:55:11 +01:00
Laurent THOMAS
5cd5f72533 case DFT12 processing with specific data organization: remove intermediate pointer 2024-10-30 17:54:58 +01:00
Robert Schmidt
f00ee9af2f review comment: to squash 2024-10-30 16:45:26 +01:00
Robert Schmidt
9395a0673e change macros for UE logging 2024-10-30 15:45:11 +00:00
Bartosz Podrygajlo
54a57bd2d6 RLC optimization - allocate SDU header and SDU data together
By allocating sdu data and sdu header together the total amount of
free/malloc calls per SDU is reduced by 1 increasing overall performance.
2024-10-30 16:03:01 +01:00
Bartosz Podrygajlo
7ae1aa21f4 RLC optimization - using function instead of function pointers
Moved some functions around so that instead of a function pointer a function
call is used. This enables inlining of functions which reduces number of function calls.
2024-10-30 16:02:50 +01:00
Laurent THOMAS
4cf2719bd9 scale in DFT16 as per normal scaling sqrt(16) = 4 2024-10-29 18:47:15 +01:00
Laurent THOMAS
f1f02ec0a1 use existing functions to retrieve (i)dft enum value 2024-10-29 18:47:15 +01:00
batuhan duyuler
edeb7b8f61 handling 1st digit of mnc in SIB1
During preparation of SIB1, first digit of MNC was not taking into account.
This leads to XRES*, RES* mismatch during Authentication Procedure between 5GCore and UE because of derived serving network names.
2024-10-29 16:43:26 +01:00
Robert Schmidt
d5cd07e37c Correct RRC log: remove trailing whitespace 2024-10-29 16:41:20 +01:00
Robert Schmidt
21d31e4359 RRC: more UE tracability through LOG_A
It is difficult to keep track of a "UE lifecycle". To make this more
easy, add LOG_A at major UE RRC messages.
2024-10-29 16:38:54 +01:00
Robert Schmidt
14d238baee RRC: keep track of UE's CellID
It will be used in the next commit
2024-10-29 16:38:07 +01:00
Robert Schmidt
a0a4096f95 Mark "gNB event" of NG connection thru LOG_A 2024-10-29 16:37:17 +01:00
Robert Schmidt
b8b921d49f Mark major "UE events" in in PHY+MAC thru LOG_A 2024-10-29 16:36:53 +01:00
Robert Schmidt
68f8ef7c7a Reduce amount of logs in L1/L2
This commit removes many logs that just show memory addresses, indices,
etc., which, I presume, do not mean anything to the "average user" and
developers alike.
2024-10-29 16:36:13 +01:00
Robert Schmidt
8cc6c0cbbb Various places: remove printf and/or transform to LOG_D 2024-10-29 16:35:47 +01:00
Robert Schmidt
83d9397002 MeasTimingConfig: only print ASN.1 when requested 2024-10-29 16:35:47 +01:00
Robert Schmidt
5180d4df74 nr-ru: remove "low-density" printf, transform rest to LOG_D
Most printf() do not show much information (like only a "X is ready",
which is not useful for subsystems). Remove those. The rest, make them
LOG_D.
2024-10-29 15:55:19 +01:00
Robert Schmidt
cbd5f1671f nr-softmodem.c: remove unnecessary printfs 2024-10-29 15:55:19 +01:00
Robert Schmidt
925566b075 module loader: remove printf(), put error into printf(stderr) 2024-10-29 15:55:19 +01:00
Robert Schmidt
85e198b178 Config module: use printf_params() to print log messages 2024-10-29 09:37:10 +01:00
Robert Schmidt
3e86e457b9 Logging: remove useless printf 2024-10-29 09:23:55 +01:00
Cedric Roux
5ffa655902 snow3g: fix array size 2024-10-28 22:16:22 +01:00
Jaroslava Fiedlerova
538c115fb7 CI: reduce RX gain in 4G pipelines to avoid false RACH attempts 2024-10-28 13:42:19 +01:00
Laurent THOMAS
6cedca1c1d fix error of grouping UE to free list for phy layer and ue to free list for fapi 2024-10-22 12:25:30 +02:00
Laurent THOMAS
9898c673d8 print rnti as hexadecimal 2024-10-22 11:05:20 +02:00
Laurent THOMAS
1614ae19e8 trace as information UE RACH steps for 4G 2024-10-22 11:05:20 +02:00
Robert Schmidt
6b32dd6e8e Avoid array buffer overflow in ue_pmch_procedures()
Adapt as code above offending line to not overflow array. Avoids UBSan
error

    openair1/SCHED_UE/phy_procedures_lte_ue.c:2983:36: runtime error: index 8 out of bounds for type 'int [8][1]'
2024-10-22 11:05:20 +02:00
Robert Schmidt
76860fd44b put_UE_in_freelist(): avoid array overflow 2024-10-22 11:05:20 +02:00
Robert Schmidt
985f44c1dd 4G RFsim docker-compose: suppress ASan leak check, lte-{ue,}softmodem is leaky 2024-10-22 11:05:20 +02:00
Robert Schmidt
712988d437 NAS message encoding: avoid unaligned access through memcpy() 2024-10-22 11:05:20 +02:00
Robert Schmidt
e94f59edb1 IES_DECODE_U16 macro: load from 16-bit aligned address
The IES_DECODE_U16 macro loads a 16 bit integer from an arbitrary
address; this can lead to reads from misaligned addresses, and undefined
behavior sanitizer warns, like, e.g., so:

    openair3/NAS/COMMON/IES/ProtocolConfigurationOptions.c:62:5: runtime error: load of misaligned address 0x7f3c24032c01 for type 'uint16_t', which requires 2 byte alignment

To fix this, first use memcpy() to load to a 16-bit aligned address,
then do the actual decoding.
2024-10-22 11:05:20 +02:00
Robert Schmidt
71bd10b4a2 docker-compose: write correct container image to use for 4G and asan 2024-10-22 11:05:20 +02:00
Robert Schmidt
cb7942d460 Build CI images for eNB/lteUE with sanitizers, and use in 4G RF sim 2024-10-22 11:05:20 +02:00
Laurent THOMAS
e48e38650d Fix various problems in 4G NAS handling
- rename as_nas_info_t member data to nas_data to have a uniq name to
  trace between complex malloc/free of this pointer
- fix, maybe not perfect, these pais od malloc/free
- remove typedef name changes across transmission of these as_nas_info_t
  over itti, as name changing makes it even more confusing
- remove globals that are likely possible races
- in as_message_decode() fix memcpy size, it is hard to understand the
  initial idea, likely the author beleives a struct of struct makes a
  intermediate pointer
- in network_api.c remove globals (static but used globally)
- remove casts that are there to hide gcc warnings on probable unaligned
  access
- remain a weird mix of packed/unpacked versions of the same typedef,
  but gcc is happy
2024-10-22 11:05:20 +02:00
Laurent THOMAS
8df8de894b get out statistic array in case the rnti is not found 2024-10-22 11:05:20 +02:00
Laurent THOMAS
972a251798 bug in code duplication 2024-10-22 11:05:20 +02:00
Laurent THOMAS
a1fc1972e1 one old bug, one regression 2024-10-22 11:05:20 +02:00
Raghavendra Dinavahi
22dd82556d New tests for nr_pbchsim 2024-10-18 14:47:26 +02:00
Raghavendra Dinavahi
586a4b76f8 Update pbchsim to work with other numerologies 2024-10-15 17:26:03 +02:00
182 changed files with 1398 additions and 11528 deletions

View File

@@ -496,28 +496,10 @@ if (ENABLE_LDPC_T2)
add_library(ldpc_t2 MODULE ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder_offload.c)
set_target_properties(ldpc_t2 PROPERTIES COMPILE_FLAGS "-DALLOW_EXPERIMENTAL_API")
target_link_libraries(ldpc_t2 ${LIBDPDK_T2_LDFLAGS} ${PMD_T2})
set(PHY_NRLDPC_CODING_T2_SRC
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_t2/nrLDPC_coding_t2.c
)
add_library(ldpc_slot_t2 MODULE ${PHY_NRLDPC_CODING_T2_SRC})
set_target_properties(ldpc_slot_t2 PROPERTIES COMPILE_FLAGS "-DALLOW_EXPERIMENTAL_API")
target_link_libraries(ldpc_slot_t2 PRIVATE ldpc_gen_HEADERS ${LIBDPDK_T2_LDFLAGS} ${PMD_T2})
endif()
##########################################################
# LDPC offload library - XDMA
##########################################################
add_boolean_option(ENABLE_LDPC_XDMA OFF "Build support for LDPC Offload to XDMA library" OFF)
if (ENABLE_LDPC_XDMA)
set(PHY_NRLDPC_CODING_XDMA_SRC
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma_offload.c
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma.c
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c
)
add_library(ldpc_xdma MODULE ${PHY_NRLDPC_CODING_XDMA_SRC})
endif()
include_directories ("${OPENAIR_DIR}/radio/COMMON")
##############################################################
@@ -856,19 +838,10 @@ add_library(ldpc_cl MODULE ${PHY_LDPC_CL_SRC} )
target_link_libraries(ldpc_cl OpenCL)
add_dependencies(ldpc_cl nrLDPC_decoder_kernels_CL)
set(PHY_NRLDPC_CODING_SEGMENT_SRC
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_decoder.c
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c
)
set(PHY_NR_CODINGIF
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_load.c
)
set(PHY_NRLDPC_CODINGIF
${OPENAIR1_DIR}/PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface_load.c
)
##############################################
# Base CUDA setting
##############################################
@@ -889,7 +862,6 @@ add_library(coding MODULE ${PHY_TURBOSRC} )
add_library(dfts MODULE ${OPENAIR1_DIR}/PHY/TOOLS/oai_dfts.c ${OPENAIR1_DIR}/PHY/TOOLS/oai_dfts_neon.c)
add_library(ldpc_slot_segment MODULE ${PHY_NRLDPC_CODING_SEGMENT_SRC})
set(PHY_SRC_COMMON
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c
@@ -1049,9 +1021,7 @@ set(PHY_SRC_UE
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch_tools.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch_coding.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch_coding_slot.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_decoding_slot.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_sch_dmrs.c
@@ -1081,7 +1051,6 @@ set(PHY_SRC_UE
${PHY_POLARSRC}
${PHY_SMALLBLOCKSRC}
${PHY_NR_CODINGIF}
${PHY_NRLDPC_CODINGIF}
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/pucch_rx.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/srs_rx.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_uci_tools_common.c
@@ -1101,9 +1070,7 @@ set(PHY_SRC_UE
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_psbch_tx.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_ulsch_coding_slot.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding_slot.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_prach_common.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_sch_dmrs.c
@@ -1139,7 +1106,6 @@ set(PHY_SRC_UE
${PHY_POLARSRC}
${PHY_SMALLBLOCKSRC}
${PHY_NR_CODINGIF}
${PHY_NRLDPC_CODINGIF}
)
@@ -2071,14 +2037,10 @@ if(E2_AGENT)
endif()
add_dependencies(nr-softmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc ldpc_slot_segment)
add_dependencies(nr-softmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc)
if (ENABLE_LDPC_T2)
add_dependencies(nr-softmodem ldpc_t2 ldpc_slot_t2)
endif()
if (ENABLE_LDPC_XDMA)
add_dependencies(nr-softmodem ldpc_xdma)
add_dependencies(nr-softmodem ldpc_t2)
endif()
# force the generation of ASN.1 so that we don't need to wait during the build
@@ -2132,20 +2094,12 @@ target_link_libraries(nr-uesoftmodem PRIVATE pthread m CONFIG_LIB rt nr_ue_phy_m
target_link_libraries(nr-uesoftmodem PRIVATE ${T_LIB})
target_link_libraries(nr-uesoftmodem PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
add_dependencies( nr-uesoftmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc ldpc_slot_segment)
add_dependencies( nr-uesoftmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc )
if (ENABLE_LDPC_CUDA)
add_dependencies(nr-uesoftmodem ldpc_cuda)
add_dependencies(nr-softmodem ldpc_cuda)
endif()
if (ENABLE_LDPC_T2)
add_dependencies(nr-uesoftmodem ldpc_t2 ldpc_slot_t2)
endif()
if (ENABLE_LDPC_XDMA)
add_dependencies(nr-uesoftmodem ldpc_xdma)
endif()
# force the generation of ASN.1 so that we don't need to wait during the build
target_link_libraries(nr-uesoftmodem PRIVATE
asn1_lte_rrc asn1_nr_rrc asn1_s1ap asn1_ngap asn1_m2ap asn1_m3ap asn1_x2ap asn1_f1ap asn1_lpp)
@@ -2301,12 +2255,8 @@ add_executable(nr_ulsim
)
if (ENABLE_LDPC_T2)
add_dependencies(nr_ulsim ldpc_t2 ldpc_slot_t2)
add_dependencies(nr_ulsim ldpc_t2)
endif()
if (ENABLE_LDPC_XDMA)
add_dependencies(nr_ulsim ldpc_xdma)
endif()
add_dependencies(nr_ulsim ldpc_slot_segment)
target_link_libraries(nr_ulsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_UE_NR MAC_NR_COMMON nr_rrc CONFIG_LIB L2_NR HASHTABLE x2ap SECURITY ngap -lz -Wl,--end-group
@@ -2373,8 +2323,7 @@ if (${T_TRACER})
PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX
L2 L2_LTE L2_NR L2_LTE_NR L2_UE NR_L2_UE L2_UE_LTE_NR MAC_NR_COMMON MAC_UE_NR ngap
CN_UTILS GTPV1U SCTP_CLIENT MME_APP LIB_NAS_UE NB_IoT SIMU OPENAIR0_LIB
ldpc_orig ldpc_optim ldpc_optim8seg ldpc_t2 ldpc_cl ldpc_cuda ldpc ldpc_slot_segment ldpc_slot_t2 ldpc_xdma
dfts config_internals nr_common)
ldpc_orig ldpc_optim ldpc_optim8seg ldpc_t2 ldpc_cl ldpc_cuda ldpc dfts config_internals nr_common)
if (TARGET ${i})
add_dependencies(${i} generate_T)
endif()

View File

@@ -7,9 +7,8 @@
<a href="https://releases.ubuntu.com/20.04/"><img src="https://img.shields.io/badge/OS-Ubuntu20-Green" alt="Supported OS Ubuntu 20"></a>
<a href="https://releases.ubuntu.com/22.04/"><img src="https://img.shields.io/badge/OS-Ubuntu22-Green" alt="Supported OS Ubuntu 22"></a>
<a href="https://releases.ubuntu.com/24.04/"><img src="https://img.shields.io/badge/OS-Ubuntu24-Green" alt="Supported OS Ubuntu 24"></a>
<a href="https://www.redhat.com/en/technologies/linux-platforms/enterprise-linux"><img src="https://img.shields.io/badge/OS-RHEL8-Green" alt="Supported OS RHEL8"></a>
<a href="https://www.redhat.com/en/technologies/linux-platforms/enterprise-linux"><img src="https://img.shields.io/badge/OS-RHEL9-Green" alt="Supported OS RELH9"></a>
<a href="https://getfedora.org/en/workstation/"><img src="https://img.shields.io/badge/OS-Fedore40-Green" alt="Supported OS Fedora 40"></a>
<a href="https://getfedora.org/en/workstation/"><img src="https://img.shields.io/badge/OS-Fedore41-Green" alt="Supported OS Fedora 41"></a>
</p>
<p align="center">

View File

@@ -0,0 +1,36 @@
apiVersion: v1
name: oai-nr-pbchsim-scs
description: A Helm subchart for nr-pbchsim network function ("Other SCS" tests)
# A chart can be either an 'application' or a 'library' chart.
#
# Application charts are a collection of templates that can be packaged into versioned archives
# to be deployed.
#
# Library charts provide useful utilities or functions for the chart developer. They're included as
# a dependency of application charts to inject those utilities and functions into the rendering
# pipeline. Library charts do not define any templates and therefore cannot be deployed.
type: application
icon: http://www.openairinterface.org/wp-content/uploads/2015/06/cropped-oai_final_logo.png
# This is the chart version. This version number should be incremented each time you make changes
# to the chart and its templates, including the app version.
version: 0.1.1
# This is the version number of the application being deployed. This version number should be
# incremented each time you make changes to the application.
appVersion: v1
keywords:
- Physical Simulator
- nr-pbchsim
- RAN
- 5G
sources:
- https://gitlab.eurecom.fr/oai/openairinterface5g
maintainers:
- name: OPENAIRINTERFACE
email: contact@openairinterface.org

View File

@@ -0,0 +1,63 @@
{{/* vim: set filetype=mustache: */}}
{{/*
Expand the name of the chart.
*/}}
{{- define "oai-nr-pbchsim-scs.name" -}}
{{- default .Chart.Name .Values.nameOverride | trunc 63 | trimSuffix "-" -}}
{{- end -}}
{{/*
Create a default fully qualified app name.
We truncate at 63 chars because some Kubernetes name fields are limited to this (by the DNS naming spec).
If release name contains chart name it will be used as a full name.
*/}}
{{- define "oai-nr-pbchsim-scs.fullname" -}}
{{- if .Values.fullnameOverride -}}
{{- .Values.fullnameOverride | trunc 63 | trimSuffix "-" -}}
{{- else -}}
{{- $name := default .Chart.Name .Values.nameOverride -}}
{{- if contains $name .Release.Name -}}
{{- .Release.Name | trunc 63 | trimSuffix "-" -}}
{{- else -}}
{{- printf "%s-%s" .Release.Name $name | trunc 63 | trimSuffix "-" -}}
{{- end -}}
{{- end -}}
{{- end -}}
{{/*
Create chart name and version as used by the chart label.
*/}}
{{- define "oai-nr-pbchsim-scs.chart" -}}
{{- printf "%s-%s" .Chart.Name .Chart.Version | replace "+" "_" | trunc 63 | trimSuffix "-" -}}
{{- end -}}
{{/*
Common labels
*/}}
{{- define "oai-nr-pbchsim-scs.labels" -}}
helm.sh/chart: {{ include "oai-nr-pbchsim-scs.chart" . }}
{{ include "oai-nr-pbchsim-scs.selectorLabels" . }}
{{- if .Chart.AppVersion }}
app.kubernetes.io/version: {{ .Chart.AppVersion | quote }}
{{- end }}
app.kubernetes.io/managed-by: {{ .Release.Service }}
{{- end -}}
{{/*
Selector labels
*/}}
{{- define "oai-nr-pbchsim-scs.selectorLabels" -}}
app.kubernetes.io/name: {{ include "oai-nr-pbchsim-scs.name" . }}
app.kubernetes.io/instance: {{ .Release.Name }}
{{- end -}}
{{/*
Create the name of the service account to use
*/}}
{{- define "oai-nr-pbchsim-scs.serviceAccountName" -}}
{{- if .Values.serviceAccount.create -}}
{{ default (include "oai-nr-pbchsim-scs.fullname" .) .Values.serviceAccount.name }}
{{- else -}}
{{ default "default" .Values.serviceAccount.name }}
{{- end -}}
{{- end -}}

View File

@@ -0,0 +1,42 @@
apiVersion: batch/v1
kind: Job
metadata:
name: {{ .Chart.Name }}
spec:
template:
metadata:
labels:
app: physim
spec:
securityContext:
{{- toYaml .Values.podSecurityContext | nindent 8 }}
{{- if .Values.imagePullSecrets }}
imagePullSecrets:
{{- toYaml . | nindent 8 }}
{{- end }}
containers:
- name: physim
image: "{{ .Values.global.image.repository }}:{{ .Values.global.image.version }}"
imagePullPolicy: {{ .Values.image.pullPolicy }}
securityContext:
{{- toYaml .Values.securityContext | nindent 12 }}
env:
- name: OPENAIR_DIR
value: /opt/oai-physim
command: ["/bin/sh", "-c"]
args:
- >
cmake_targets/autotests/run_exec_autotests.bash -g "nr_pbchsim.otherSCS" -d bin/ &&
echo "FINISHED" && sleep infinity
dnsPolicy: ClusterFirst
restartPolicy: Never
schedulerName: default-scheduler
serviceAccountName: {{ .Values.global.serviceAccountName }}
terminationGracePeriodSeconds: 30
{{- if .Values.global.nodeSelector}}
nodeSelector:
{{- toYaml .Values.global.nodeSelector | nindent 12 }}
{{- end }}
{{- if .Values.global.nodeName.nrpbchsim273rb}}
nodeName: {{ .Values.global.nodeName.nrpbchsim273rb }}
{{- end }}

View File

@@ -0,0 +1,48 @@
# Default values for oai-nr-pbchsim-scs
# This is a YAML-formatted file.
# Declare variables to be passed into your templates.
replicaCount: 1
image:
# pullPolicy: IfNotPresent or Never or Always
pullPolicy: Always
imagePullSecrets: []
nameOverride: ""
fullnameOverride: ""
serviceAccount:
# Specifies whether a service account should be created
create: true
# Annotations to add to the service account
annotations: {}
# The name of the service account to use.
# If not set and create is true, a name is generated using the fullname template
name: "oai-nr-pbchsim-scs"
podSecurityContext:
runAsUser: 0
runAsGroup: 0
securityContext:
privileged: false
resources: {}
# We usually recommend not to specify default resources and to leave this as a conscious
# choice for the user. This also increases chances charts run on environments with little
# resources, such as Minikube. If you do want to specify resources, uncomment the following
# lines, adjust them as necessary, and remove the curly braces after 'resources:'.
# limits:
# cpu: 100m
# memory: 128Mi
# requests:
# cpu: 100m
# memory: 128Mi
nodeSelector: {}
tolerations: []
affinity: {}

View File

@@ -27,6 +27,7 @@ global:
nrpbschsim106rb: dedale
nrpbchsim217rb: dedale
nrpbchsim273rb: dedale
nrpbchsimscs: dedale
nrpsbchsim: dedale
nrprachsim: dedale
nrpucchsim: dedale

View File

@@ -73,9 +73,9 @@ then
do
IS_NFAPI=`echo $FILE | grep -E -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext" || true`
IS_OAI_LICENCE_PRESENT=`grep -E -c "OAI Public License" $FILE || true`
IS_BSD_LICENCE_PRESENT=`grep -E -c "the terms of the BSD Licence|License-Identifier: BSD-2-Clause|License-Identifier: BSD-3-Clause" $FILE || true`
IS_BSD_LICENCE_PRESENT=`grep -E -c "the terms of the BSD Licence|License-Identifier: BSD-2-Clause" $FILE || true`
IS_MIT_LICENCE_PRESENT=`grep -E -c "MIT License" $FILE || true`
IS_EXCEPTION=`echo $FILE | grep -E -c "common/utils/collection/tree.h|common/utils/collection/queue.h|openair2/UTIL/OPT/packet-rohc.h|openair3/NAS/COMMON/milenage.h|openair1/PHY/CODING/crc.h|openair1/PHY/CODING/crcext.h|openair1/PHY/CODING/types.h" || true`
IS_EXCEPTION=`echo $FILE | grep -E -c "common/utils/collection/tree.h|common/utils/collection/queue.h|openair2/UTIL/OPT/packet-rohc.h|openair3/NAS/COMMON/milenage.h|openair1/PHY/CODING/crc.h|openair1/PHY/CODING/crcext.h|openair1/PHY/CODING/types.h|openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder_offload.c|openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_offload.h" || true`
if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ] && [ $IS_MIT_LICENCE_PRESENT -eq 0 ]
then
if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ]
@@ -184,9 +184,9 @@ do
then
IS_NFAPI=`echo $FULLFILE | grep -E -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext" || true`
IS_OAI_LICENCE_PRESENT=`grep -E -c "OAI Public License" $FULLFILE || true`
IS_BSD_LICENCE_PRESENT=`grep -E -c "the terms of the BSD Licence|License-Identifier: BSD-2-Clause|License-Identifier: BSD-3-Clause" $FULLFILE || true`
IS_BSD_LICENCE_PRESENT=`grep -E -c "the terms of the BSD Licence|License-Identifier: BSD-2-Clause" $FULLFILE || true`
IS_MIT_LICENCE_PRESENT=`grep -E -c "MIT License" $FULLFILE || true`
IS_EXCEPTION=`echo $FULLFILE | grep -E -c "common/utils/collection/tree.h|common/utils/collection/queue.h|openair2/UTIL/OPT/packet-rohc.h|openair3/NAS/COMMON/milenage.h|openair1/PHY/CODING/crc.h|openair1/PHY/CODING/crcext.h|openair1/PHY/CODING/types.h" || true`
IS_EXCEPTION=`echo $FULLFILE | grep -E -c "common/utils/collection/tree.h|common/utils/collection/queue.h|openair2/UTIL/OPT/packet-rohc.h|openair3/NAS/COMMON/milenage.h|openair1/PHY/CODING/crc.h|openair1/PHY/CODING/crcext.h|openair1/PHY/CODING/types.h|openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_decoder_offload.c|openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_offload.h" || true`
if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ] && [ $IS_MIT_LICENCE_PRESENT -eq 0 ]
then
if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ]

View File

@@ -52,7 +52,7 @@ import cls_oaicitest
# Helper functions used here and in other classes
# (e.g., cls_cluster.py)
#-----------------------------------------------------------
IMAGES = ['oai-enb', 'oai-lte-ru', 'oai-lte-ue', 'oai-gnb', 'oai-nr-cuup', 'oai-gnb-aw2s', 'oai-nr-ue', 'oai-gnb-asan', 'oai-nr-ue-asan', 'oai-nr-cuup-asan', 'oai-gnb-aerial', 'oai-gnb-fhi72']
IMAGES = ['oai-enb', 'oai-lte-ru', 'oai-lte-ue', 'oai-gnb', 'oai-nr-cuup', 'oai-gnb-aw2s', 'oai-nr-ue', 'oai-enb-asan', 'oai-gnb-asan', 'oai-lte-ue-asan', 'oai-nr-ue-asan', 'oai-nr-cuup-asan', 'oai-gnb-aerial', 'oai-gnb-fhi72']
def CreateWorkspace(host, sourcePath, ranRepository, ranCommitID, ranTargetBranch, ranAllowMerge):
if ranCommitID == '':
@@ -208,7 +208,9 @@ def WriteEnvFile(ssh, services, wd, tag):
ret = ssh.run(f'docker image inspect {checkimg}', reportNonZero=False)
if ret.returncode == 0:
logging.info(f"detected pulled image {checkimg}")
if "oai-gnb" in image: envs["GNB_IMG"] = "oai-gnb-asan"
if "oai-enb" in image: envs["ENB_IMG"] = "oai-enb-asan"
elif "oai-gnb" in image: envs["GNB_IMG"] = "oai-gnb-asan"
elif "oai-lte-ue" in image: envs["LTEUE_IMG"] = "oai-lte-ue-asan"
elif "oai-nr-ue" in image: envs["NRUE_IMG"] = "oai-nr-ue-asan"
elif "oai-nr-cuup" in image: envs["NRCUUP_IMG"] = "oai-nr-cuup-asan"
else: logging.warning("undetected image format {image}, cannot use asan")
@@ -415,7 +417,9 @@ class Containerize():
imageNames.append(('oai-gnb-aerial', 'gNB.aerial', 'oai-gnb-aerial', ''))
# Building again the 5G images with Address Sanitizer
imageNames.append(('ran-build', 'build', 'ran-build-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('oai-enb', 'eNB', 'oai-enb-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('oai-gnb', 'gNB', 'oai-gnb-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('oai-lte-ue', 'lteUE', 'oai-lte-ue-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('oai-nr-ue', 'nrUE', 'oai-nr-ue-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('oai-nr-cuup', 'nr-cuup', 'oai-nr-cuup-asan', '--build-arg "BUILD_OPTION=--sanitize"'))
imageNames.append(('ran-build-fhi72', 'build.fhi72', 'ran-build-fhi72', ''))
@@ -783,7 +787,7 @@ class Containerize():
HTML.CreateHtmlTestRowQueue("Build unit tests", 'OK', [dockerfile])
# it worked, build and execute tests, and close connection
ret = cmd.run(f'docker run -a STDOUT -e LD_LIBRARY_PATH=. --rm ran-unittests:{baseTag} ctest --output-on-failure --no-label-summary -j$(nproc)')
ret = cmd.run(f'docker run -a STDOUT --workdir /oai-ran/build/ --env LD_LIBRARY_PATH=/oai-ran/build/ --rm ran-unittests:{baseTag} ctest --output-on-failure --no-label-summary -j$(nproc)')
cmd.run(f'docker rmi ran-unittests:{baseTag}')
build_log_name = f'build_log_{self.testCase_id}'
CopyLogsToExecutor(cmd, lSourcePath, build_log_name)
@@ -846,6 +850,11 @@ class Containerize():
mySSH.close()
HTML.CreateHtmlTestRow(msg, 'KO', CONST.ALL_PROCESSES_OK)
return False
# Creating a develop tag on the local private registry
if not self.ranAllowMerge:
mySSH.command(f'docker image tag {image}:{orgTag} {imagePrefix}/{image}:develop', '\$', 5)
mySSH.command(f'docker push {imagePrefix}/{image}:develop', '\$', 120)
mySSH.command(f'docker rmi {imagePrefix}/{image}:develop', '\$', 120)
mySSH.command(f'docker rmi {imagePrefix}/{imageTag} {image}:{orgTag}', '\$', 30)
mySSH.command(f'docker logout {imagePrefix}', '\$', 5)

View File

@@ -163,7 +163,7 @@ class PhySim:
mySSH.command('oc get pods -o wide -l app=physim | tee -a cmake_targets/log/physim_pods_summary.txt', '\$', 30, resync=True)
running_count = mySSH.getBefore().count('Running')
completed_count = mySSH.getBefore().count('Completed')
if (running_count + completed_count) == 22:
if (running_count + completed_count) == 23:
logging.debug('\u001B[1m Running the physim test Scenarios\u001B[0m')
isRunning = True
podNames = re.findall('oai-[\S\d\w]+', mySSH.getBefore())

View File

@@ -228,7 +228,7 @@ RUs = (
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 0;
att_rx = 6;
eNB_instances = [0];
}
);

View File

@@ -191,7 +191,7 @@ RUs = (
nb_tx = 1
nb_rx = 1
att_tx = 6
att_rx = 6;
att_rx = 12;
bands = [38];
max_pdschReferenceSignalPower = -27;
max_rxgain = 125;

View File

@@ -191,7 +191,7 @@ RUs = (
nb_tx = 1
nb_rx = 1
att_tx = 6
att_rx = 6;
att_rx = 12;
bands = [38];
max_pdschReferenceSignalPower = -27;
max_rxgain = 125;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -224,7 +224,7 @@ RUs =
nb_tx = 1
nb_rx = 1
att_tx = 3
att_rx = 0;
att_rx = 6;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 115;

View File

@@ -9,7 +9,7 @@ uicc0:
#/* To be included in main config file when */
#/* channel modelisation is used (rfsimulator with chanmod options enabled) */
channelmod:
max_chan: 10;
max_chan: 10
modellist: modellist_rfsimu_1
modellist_rfsimu_1:
- model_name: rfsimu_channel_enB0

View File

@@ -31,7 +31,6 @@ RUN apt-get update && \
DEBIAN_FRONTEND=noninteractive apt-get upgrade --yes && \
DEBIAN_FRONTEND=noninteractive apt-get install --yes \
libgtest-dev \
libbenchmark-dev \
libyaml-cpp-dev
RUN rm -Rf /oai-ran
@@ -39,4 +38,4 @@ WORKDIR /oai-ran
COPY . .
WORKDIR /oai-ran/build
RUN cmake -GNinja -DENABLE_TESTS=ON -DCMAKE_BUILD_TYPE=Debug -DSANITIZE_ADDRESS=True .. && ninja tests nr_ulsim nr_dlsim dfts ldpc
RUN cmake -GNinja -DENABLE_TESTS=ON -DCMAKE_BUILD_TYPE=Debug -DSANITIZE_ADDRESS=True .. && ninja tests

View File

@@ -53,7 +53,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="000011">

View File

@@ -44,7 +44,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="800813">
<class>Create_Workspace</class>

View File

@@ -48,7 +48,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="800813">
<class>Create_Workspace</class>

View File

@@ -48,7 +48,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="800813">
<class>Create_Workspace</class>

View File

@@ -41,7 +41,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="800813">
<class>Create_Workspace</class>

View File

@@ -41,7 +41,7 @@
<class>Pull_Local_Registry</class>
<desc>Pull Images from Local Registry</desc>
<test_svr_id>0</test_svr_id>
<images_to_pull>oai-enb oai-lte-ue</images_to_pull>
<images_to_pull>oai-enb-asan oai-lte-ue-asan</images_to_pull>
</testCase>
<testCase id="800813">
<class>Create_Workspace</class>

View File

@@ -178,7 +178,7 @@ services:
retries: 5
oai_enb:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: l2sim4g-oai-enb
network_mode: "host"
@@ -210,7 +210,7 @@ services:
retries: 5
oai_ue1:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: l2sim4g-oai-lte-ue1
network_mode: "host"
@@ -229,7 +229,7 @@ services:
retries: 5
oai_ue2:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: l2sim4g-oai-lte-ue2
network_mode: "host"

View File

@@ -178,7 +178,7 @@ services:
retries: 5
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -186,6 +186,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band7.25prb.rfsim.conf:/opt/oai-enb/etc/enb.conf
@@ -196,7 +197,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -206,6 +207,7 @@ services:
- "10000"
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim -C 2680000000 -r 25 --ue-rxgain 140 --ue-txgain 120 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/lteue.usim-ci.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -1,6 +1,6 @@
services:
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -8,6 +8,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --log_config.global_log_options level,nocolor,time --noS1
volumes:
- ../../conf_files/enb.band7.25prb.rfsim.nos1.conf:/opt/oai-enb/etc/enb.conf
@@ -18,7 +19,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -28,6 +29,7 @@ services:
- "10000"
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim -C 2680000000 -r 25 --ue-rxgain 140 --ue-txgain 120 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time --noS1
volumes:
- ../../conf_files/lteue.usim-ci.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -178,7 +178,7 @@ services:
retries: 5
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -186,6 +186,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band7.50prb.rfsim.conf:/opt/oai-enb/etc/enb.conf
@@ -196,7 +197,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -206,6 +207,7 @@ services:
- "10000"
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim -C 2680000000 -r 50 --ue-rxgain 140 --ue-txgain 120 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/lteue.usim-ci.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -178,7 +178,7 @@ services:
retries: 5
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -186,6 +186,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band7.100prb.rfsim.conf:/opt/oai-enb/etc/enb.conf
@@ -196,7 +197,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -206,6 +207,7 @@ services:
- "10000"
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim -C 2680000000 -r 100 --ue-rxgain 140 --ue-txgain 120 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/lteue.usim-ci.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -1,6 +1,6 @@
services:
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -8,6 +8,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --noS1 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band7.tm1.25prb.rfsim.mbms.conf:/opt/oai-enb/etc/enb.conf
@@ -18,7 +19,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -26,6 +27,7 @@ services:
ipv4_address: 192.168.61.30
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: -C 2680000000 -r 25 --ue-rxgain 140 --ue-txgain 120 --rfsim --noS1 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time --noS1
volumes:
- ../../conf_files/lteue.usim-mbs.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -1,6 +1,6 @@
services:
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -8,6 +8,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --noS1 --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band7.tm1.25prb.rfsim.mbms.conf:/opt/oai-enb/etc/enb.conf
@@ -18,7 +19,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -31,6 +32,7 @@ services:
environment:
TZ: Europe/Paris
HOSTNAME: oai_ue0
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: -C 2680000000 -r 25 --ue-rxgain 140 --ue-txgain 120 --rfsim --noS1 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time --noS1
volumes:
- ../../conf_files/lteue.usim-mbs.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -178,7 +178,7 @@ services:
retries: 5
oai_enb0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-enb:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${ENB_IMG:-oai-enb}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-enb
networks:
@@ -186,6 +186,7 @@ services:
ipv4_address: 192.168.61.20
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/enb.band38.25prb.rfsim.conf:/opt/oai-enb/etc/enb.conf
@@ -196,7 +197,7 @@ services:
retries: 5
oai_ue0:
image: ${REGISTRY:-oaisoftwarealliance}/oai-lte-ue:${TAG:-develop}
image: ${REGISTRY:-oaisoftwarealliance}/${LTEUE_IMG:-oai-lte-ue}:${TAG:-develop}
privileged: true
container_name: rfsim4g-oai-lte-ue0
networks:
@@ -206,6 +207,7 @@ services:
- "10000"
environment:
TZ: Europe/Paris
ASAN_OPTIONS: detect_leaks=0
USE_ADDITIONAL_OPTIONS: --rfsim -T -C 2605000000 -r 25 --ue-rxgain 140 --ue-txgain 120 --rfsimulator.serveraddr 192.168.61.20 --log_config.global_log_options level,nocolor,time
volumes:
- ../../conf_files/lteue.usim-ci.conf:/opt/oai-lte-ue/etc/ue_usim.conf

View File

@@ -149,6 +149,18 @@
<nruns>3</nruns>
</testCase>
<testCase id="nr_pbchsim.otherSCS">
<desc>nr_pbchsim Test cases. (Test1: PBCH-only, 15Khz, 5Mhz),
(Test2: PBCH-only, 120Khz, 50Mhz)</desc>
<main_exec>nr_pbchsim</main_exec>
<main_exec_args>-s-10 -S-8 -n10 -m0 -R25
-s-10 -S-8 -n10 -m3 -R32</main_exec_args>
<tags>test1 test2</tags>
<search_expr_true>PBCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
</testCase>
<testCase id="nr_dlsim.basic">
<desc>nr_dlsim Test cases. (Test1: 106 PRB),
(Test2: 217 PRB),

View File

@@ -46,7 +46,7 @@ BUILD_DOXYGEN=0
DISABLE_HARDWARE_DEPENDENCY="False"
CMAKE_BUILD_TYPE="RelWithDebInfo"
CMAKE_CMD="$CMAKE"
OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope ldpc_cuda ldpc_t2 ldpc_xdma websrv oai_iqplayer imscope"
OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope ldpc_cuda ldpc_t2 websrv oai_iqplayer imscope"
TARGET_LIST=""
function print_help() {
@@ -99,31 +99,18 @@ Options:
Selects the transport protocol type, options: None, Ethernet, benetel4g, benetel5g, oran_fhlib_5g
-P | --phy_simulators
Makes the unitary tests Layer 1 simulators
-S | --core_simulators
Makes the core security features unitary simulators
-s | --check
runs a set of auto-tests based on simulators and several compilation tests
--run-group
runs only specified test cases specified here. This flag is only valid with -s
-V | --vcd
Adds a debgging facility to the binary files: GUI with major internal synchronization events
-x | --xforms
Will compile with software oscilloscope features
--verbose-compile
Shows detailed compilation instructions in makefile
--build-doxygen
Builds doxygen based documentation.
--build-coverity-scan
Builds Coverity-Scan objects for upload
--disable-deadline
Disables deadline scheduler of Linux kernel (>=3.14.x).
--trace-asn1c-enc-dec
Output asn1c logging traces via OAI logging system.
--enable-deadline
Enable deadline scheduler of Linux kernel (>=3.14.x).
--disable-cpu-affinity
Disables CPU Affinity between UHD/TX/RX Threads (Valid only when deadline scheduler is disabled). By defaulT, CPU Affinity is enabled when not using deadline scheduler. It is enabled only with >2 CPUs. For eNB, CPU_0-> Device library (UHD), CPU_1->TX Threads, CPU_2...CPU_MAX->Rx Threads. For UE, CPU_0->Device Library(UHD), CPU_1..CPU_MAX -> All the UE threads
--enable-cpu-affinity
--enable-LTTNG
Enable LTTNG log. While lttng is enabled, T-Tracer will be disabled
--disable-T-Tracer
@@ -146,8 +133,6 @@ Options:
Disable AVX512 intrinsics whatever processor capability is
--noavx2
Disable AVX2 intrinsics whatever processor capability is
-k | --skip-shared-libraries
Skip build for shared libraries to reduce compilation time when building frequently for debugging purposes
--ninja
Tell cmake to use the Ninja build system. Without, will generate make files
--sanitize
@@ -339,9 +324,6 @@ function main() {
echo_info "Setting gtk-wave output"
CMAKE_CMD="$CMAKE_CMD -DENABLE_VCD_FIFO=True"
shift;;
-x | --xforms)
echo_info "Will generate the software oscilloscope features"
shift;;
--verbose-compile)
VERBOSE_COMPILE=1
echo_info "Will compile with verbose instructions"

View File

@@ -107,6 +107,7 @@ check_supported_distribution() {
"ubuntu22.04") return 0 ;;
"ubuntu20.04") return 0 ;;
"debian11") return 0 ;;
"fedora41") return 0 ;;
"fedora40") return 0 ;;
"rhel8.2") return 0 ;;
"rhel8.3") return 0 ;;
@@ -612,13 +613,11 @@ check_install_oai_software() {
git \
pkgconfig \
libconfig-devel \
libffi-devel \
lksctp-tools \
lksctp-tools-devel \
libtool \
ninja-build \
make \
openssl \
openssl-devel \
patch \
readline-devel \

View File

@@ -302,7 +302,7 @@ configmodule_interface_t *load_configmodule(int argc,
}
static configmodule_interface_t *cfgptr;
if (cfgptr)
printf("ERROR: Call load_configmodule more than one time\n");
fprintf(stderr, "ERROR: Call load_configmodule more than one time\n");
// The macros are not thread safe print_params and similar
cfgptr = calloc(sizeof(configmodule_interface_t), 1);
@@ -369,8 +369,7 @@ configmodule_interface_t *load_configmodule(int argc,
if (strstr(cfgparam,CONFIG_CMDLINEONLY) == NULL) {
i=load_config_sharedlib(cfgptr);
if (i == 0) {
printf("[CONFIG] config module %s loaded\n",cfgmode);
if (i == 0) {
int idx = config_paramidx_fromname(Config_Params, sizeofArray(Config_Params), CONFIGP_DEBUGFLAGS);
Config_Params[idx].uptr = &(cfgptr->rtflags);
idx = config_paramidx_fromname(Config_Params, sizeofArray(Config_Params), CONFIGP_TMPDIR);
@@ -387,7 +386,7 @@ configmodule_interface_t *load_configmodule(int argc,
cfgptr->end = (configmodule_endfunc_t)nooptfunc;
}
printf("[CONFIG] debug flags: 0x%08x\n", cfgptr->rtflags);
printf_params(cfgptr, "[CONFIG] debug flags: 0x%08x\n", cfgptr->rtflags);
if (modeparams != NULL) free(modeparams);
@@ -413,7 +412,7 @@ void write_parsedcfg(configmodule_interface_t *cfgptr)
cfgptr->status->num_write);
}
if (cfgptr->write_parsedcfg != NULL) {
printf("[CONFIG] calling config module write_parsedcfg function...\n");
printf_params(cfgptr, "[CONFIG] calling config module write_parsedcfg function...\n");
cfgptr->write_parsedcfg(cfgptr);
}
}
@@ -425,12 +424,11 @@ void end_configmodule(configmodule_interface_t *cfgptr)
if (cfgptr != NULL) {
write_parsedcfg(cfgptr);
if (cfgptr->end != NULL) {
printf ("[CONFIG] calling config module end function...\n");
printf_params(cfgptr, "[CONFIG] calling config module end function...\n");
cfgptr->end(cfgptr);
}
pthread_mutex_lock(&cfgptr->memBlocks_mutex);
printf ("[CONFIG] free %u config value pointers\n",cfgptr->numptrs);
for(int i=0; i<cfgptr->numptrs ; i++) {
if (cfgptr->oneBlock[i].ptrs != NULL && cfgptr->oneBlock[i].ptrsAllocated== true && cfgptr->oneBlock[i].toFree) {

View File

@@ -461,13 +461,11 @@ int config_libconfig_get(configmodule_interface_t *cfg, paramdef_t *cfgoptions,
} /* switch on param type */
if( notfound == 1) {
printf("[LIBCONFIG] %s not found in %s ", cfgpath,libconfig_privdata.configfile );
fprintf(stderr, "[LIBCONFIG] %s not found in %s ", cfgpath, libconfig_privdata.configfile);
if ( (cfgoptions[i].paramflags & PARAMFLAG_MANDATORY) != 0) {
fatalerror=1;
printf(" mandatory parameter missing\n");
} else {
printf("\n");
fprintf(stderr, " mandatory parameter missing\n");
}
} else {
if (defval == 1) {
@@ -570,8 +568,8 @@ int config_libconfig_init(configmodule_interface_t *cfg)
}
const char *incp = config_get_include_dir (&(libconfig_privdata.cfg)) ;
printf("[LIBCONFIG] Path for include directive set to: %s\n", (incp!=NULL)?incp:"libconfig defaults");
printf_params(cfg, "[LIBCONFIG] Path for include directive set to: %s\n", (incp != NULL) ? incp : "libconfig defaults");
/* set convertion option to allow integer to float conversion*/
config_set_auto_convert (&(libconfig_privdata.cfg), CONFIG_TRUE);
/* Read the file. If there is an error, report it and exit. */
@@ -582,7 +580,7 @@ int config_libconfig_init(configmodule_interface_t *cfg)
config_error_line(&(libconfig_privdata.cfg)),
config_error_text(&(libconfig_privdata.cfg)));
config_destroy(&(libconfig_privdata.cfg));
printf( "\n");
fprintf(stderr, "\n");
free(tmppath);
return -1;
}
@@ -623,11 +621,11 @@ void config_libconfig_write_parsedcfg(configmodule_interface_t *cfg)
config_error_line(&(libconfig_privdata.runtcfg)),
config_error_text(&(libconfig_privdata.runtcfg)));
} else {
printf("[LIBCONFIG] file %s created successfully\n", cfg->status->debug_cfgname);
printf_params(cfg, "[LIBCONFIG] file %s created successfully\n", cfg->status->debug_cfgname);
}
free(fname);
} else {
printf("[LIBCONFIG] Cannot create config file after parsing: CONFIG_SAVERUNCFG flag not specified\n");
printf_params(cfg, "[LIBCONFIG] Cannot create config file after parsing: CONFIG_SAVERUNCFG flag not specified\n");
}
}

View File

@@ -517,7 +517,6 @@ int logInit (void)
"Invalid log options: time and wall_clock both set but are mutually exclusive\n");
g_log->flag = g_log->flag | FLAG_INITIALIZED;
printf("log init done\n");
return 0;
}
@@ -946,7 +945,6 @@ int logInit_log_mem (char * filename)
return -1;
}
pthread_create(&log_mem_thread, NULL, (void *(*)(void *))flush_mem_to_file, (void *)NULL);
printf("log init done\n");
return 0;
}

View File

@@ -49,7 +49,7 @@ void loader_init(void) {
loader_data.mainexec_buildversion = OAI_PACKAGE_VERSION;
int ret = config_get(config_get_if(), LoaderParams, sizeofArray(LoaderParams), LOADER_CONFIG_PREFIX);
if (ret <0) {
printf("[LOADER] configuration couldn't be performed via config module, parameters set to default values\n");
fprintf(stderr, "[LOADER] configuration couldn't be performed via config module, parameters set to default values\n");
if (loader_data.shlibpath == NULL) {
loader_data.shlibpath=DEFAULT_PATH;
}
@@ -136,12 +136,9 @@ int load_module_version_shlib(char *modname, char *version, loader_shlibfunc_t *
}
shlib_path = loader_format_shlibpath(modname, version);
printf("shlib_path %s\n", shlib_path);
for (int i = 0; i < loader_data.numshlibs; i++) {
if (strcmp(loader_data.shlibs[i].name, modname) == 0) {
printf("[LOADER] library %s has been loaded previously, reloading function pointers\n",
shlib_path);
lib_idx = i;
break;
}
@@ -165,7 +162,6 @@ int load_module_version_shlib(char *modname, char *version, loader_shlibfunc_t *
goto load_module_shlib_exit;
}
printf("[LOADER] library %s successfully loaded\n", shlib_path);
afname = malloc(strlen(modname)+15);
if (!afname) {
fprintf(stderr, "[LOADER] unable to allocate memory for library %s\n", shlib_path);

View File

@@ -74,6 +74,11 @@ If DPDK library was installed into custom path, you have to point to the right d
```
export PKG_CONFIG_PATH=/opt/dpdk-t2/lib64/pkgconfig/:$PKG_CONFIG_PATH
```
## Setup of T2-related DPDK EAL parameters
To configure T2-related DPDK Environment Abstraction Layer (EAL) parameters, you can set the following parameters via the command line:
- `ldpc_offload.dpdk_dev` - **mandatory** parameter, specifies PCI address of the T2 card. PCI address of the T2 card can be detected by `lspci | grep "Xilinx"` command.
- `ldpc_offload.dpdk_cores_list` - CPU cores assigned to DPDK for T2 processing, by default set to *11-12*. Ensure that the CPU cores specified in *ldpc_offload.dpdk_cores_list* are available and not used by other processes to avoid conflicts.
- `ldpc_offload.dpdk_prefix` - DPDK shared data file prefix, by default set to *b6*
# OAI Build
OTA deployment is precisely described in the following tutorial:
@@ -97,71 +102,11 @@ cd cmake_targets
./build_oai -w USRP --ninja --gNB -P --build-lib "ldpc_t2" -C
```
Shared object file *libldpc_slot_t2.so* is created during the compilation. This object is conditionally compiled. Selection of the library to compile is done using *--build-lib ldpc_t2*.
Shared object file *libldpc_t2.so* is created during the compilation. This object is conditionally compiled. Selection of the library to compile is done using *--build-lib ldpc_t2*.
*Required poll mode driver has to be present on the host machine and required DPDK version has to be installed on the host, prior to the build of OAI*
# Setup of T2-related DPDK EAL parameters
To configure T2-related DPDK Environment Abstraction Layer (EAL) parameters, you can set the following parameters via the command line of PHY simulators or softmodem:
- `nrLDPC_coding_t2.dpdk_dev` - **mandatory** parameter, specifies PCI address of the T2 card. PCI address of the T2 card can be detected by `lspci | grep "Xilinx"` command.
- `nrLDPC_coding_t2.dpdk_core_list` - **mandatory** parameter, specifies CPU cores assigned to DPDK for T2 processing. Ensure that the CPU cores specified in *nrLDPC_coding_t2.dpdk_core_list* are available and not used by other processes to avoid conflicts.
- `nrLDPC_coding_t2.dpdk_prefix` - DPDK shared data file prefix, by default set to *b6*.
**Note:** These parameters can also be provided in a configuration file:
```
nrLDPC_coding_t2 : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};
loader : {
ldpc : {
shlibversion : "_slot_t2";
};
};
```
# 5G PHY simulators
## nr_ulsim test
Offload of the channel decoding to the T2 card is in nr_ulsim specified by *--loader.ldpc.shlibversion _slot_t2* option. Example command for running nr_ulsim with LDPC decoding offload to the T2 card:
```
cd ~/openairinterface5g
source oaienv
cd cmake_targets/ran_build/build
sudo ./nr_ulsim -n100 -s20 -m20 -r273 -R273 --loader.ldpc.shlibversion _slot_t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
```
## nr_dlsim test
Offload of the channel encoding to the AMD Xilinx T2 card is in nr_dlsim specified by *-c* option. Example command for running nr_dlsim with LDPC encoding offload to the T2 card:
```
cd ~/openairinterface5g
source oaienv
cd cmake_targets/ran_build/build
sudo ./nr_dlsim -n300 -s30 -R 106 -e 27 --loader.ldpc.shlibversion _slot_t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
```
# OTA test
Offload of the channel encoding and decoding to the AMD Xilinx T2 card is enabled by *--loader.ldpc.shlibversion _slot_t2* option.
## Run OAI gNB with USRP B210
```
cd ~/openairinterface5g
source oaienv
cd cmake_targets/ran_build/build
sudo ./nr-softmodem --sa -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --loader.ldpc.shlibversion _slot_t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1
```
# Alternative legacy implementation
The current implementation of LDPC coding with T2 described above is new and may still comprise some regression in comparison to the legacy implementation besides all the test and improvements performed.
Therefore, the legacy implementation remains available.
It is compiled at the same time as the current implementation and it can be selected with the arguments described below.
## Setup of T2-related DPDK EAL parameters
To configure T2-related DPDK Environment Abstraction Layer (EAL) parameters, you can set the following parameters via the command line:
- `ldpc_offload.dpdk_dev` - **mandatory** parameter, specifies PCI address of the T2 card. PCI address of the T2 card can be detected by `lspci | grep "Xilinx"` command.
- `ldpc_offload.dpdk_cores_list` - CPU cores assigned to DPDK for T2 processing, by default set to *11-12*. Ensure that the CPU cores specified in *ldpc_offload.dpdk_cores_list* are available and not used by other processes to avoid conflicts.
- `ldpc_offload.dpdk_prefix` - DPDK shared data file prefix, by default set to *b6*
## nr_ulsim test
Offload of the channel decoding to the T2 card is in nr_ulsim specified by *-o* option. Example command for running nr_ulsim with LDPC decoding offload to the T2 card:
```
@@ -179,8 +124,10 @@ cd cmake_targets/ran_build/build
sudo ./nr_dlsim -n300 -s30 -R 106 -e 27 -c --ldpc_offload.dpdk_dev 01:00.0
```
## Run OAI gNB with USRP B210
# OTA test
Offload of the channel encoding and decoding to the AMD Xilinx T2 card is enabled by *--ldpc-offload-enable* option.
## Run OAI gNB with USRP B210
```
cd ~/openairinterface5g
source oaienv

View File

@@ -1,155 +0,0 @@
[TOC]
This documentation aims to provide a tutorial for Xilinx FPGA PCIe-XDMA integration into OAI and its usage. It can offload LDPC decoding to FPGA.
# Requirements
- XDMA driver
# XDMA Driver Build & Install
The *xdma_driver* directory contains the following:
```bash
xdma_driver
├── cmake
├── FPGA_TEST_datasheet.txt
├── include
├── libfpga_0720_vt.so
├── libfpga_8038_vt.so
├── libfpga_ldpc.a
├── libTHIRD_PARTY.a
├── nr_ldpc_decoding_pym.h
├── README.md
├── tests
├── xdma
└── xdma_diag.h
```
Before building the driver, ensure that your system recognizes the Xilinx device. You can check this using the `lspci` command:
```bash
$ lspci | grep Xilinx
01:00.0 Serial controller: Xilinx Corporation Device 8038
```
Building and Installing the Driver
```
cd xdma_driver/xdma
sudo make clean
sudo make install
cd xdma_driver/tests
sudo ./load_driver.sh
```
# OAI Build
```bash
# Get openairinterface5g source code
git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git ~/openairinterface5g
cd ~/openairinterface5g
# Install OAI dependencies
cd ~/openairinterface5g/cmake_targets
./build_oai -I
# Build OAI gNB & UE
cd ~/openairinterface5g
source oaienv
cd cmake_targets
./build_oai --ninja -w SIMU --gNB --nrUE -P --build-lib "ldpc_xdma" -C -c
```
Shared object file *libldpc_xdma.so* is created during the compilation. This object is conditionally compiled. Selection of the library to compile is done using `--build-lib ldpc_xdma`.
# 5G PHY simulators
The simulated test uses the option `--loader.ldpc.shlibversion _xdma` to select the XDMA version for loading into the LDPC interface. Additionally, the option `--nrLDPC_coding_xdma.num_threads_prepare` is used to specify the number of threads for preparing data before the LDPC processing, specifically for the deinterleaving and rate matching parts.
Another way to activate the feature is to add the `xdma.conf` file with the following content:
```
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};
```
and use option `-O xdma.conf`.
## nr_ulsim test
Example command for running nr_ulsim with LDPC decoding offload to the FPGA:
```bash
cd ~/openairinterface5g/cmake_targets/ran_build/build
sudo ./nr_ulsim -n100 -m28 -r273 -R273 -s22 -I10 -C8 -P --loader.ldpc.shlibversion _xdma --nrLDPC_coding_xdma.num_threads_prepare 2
```
or
```
sudo ./nr_ulsim -n100 -m28 -r273 -R273 -s22 -I10 -C8 -P -O xdma.conf
```
# Run
Both gNB and nrUE use the option `--loader.ldpc.shlibversion _xdma` to select the XDMA version for loading into the LDPC interface and `--nrLDPC_coding_xdma.num_threads_prepare` to specify the number of threads for preparing data before the LDPC processing, specifically for the deinterleaving and rate matching parts.
Another way to activate the feature is to add the following content to the `.conf` file you want to use:
```
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};
```
and use option `-O *.conf`.
## gNB
Example command using rfsim:
```bash
cd ~/openairinterface5g/cmake_targets/ran_build/build
sudo ./nr-softmodem --sa --rfsim --log_config.global_log_options level,nocolor,time -O ../../../ci-scripts/conf_files/gnb.sa.band78.106prb.rfsim.conf --loader.ldpc.shlibversion _xdma --nrLDPC_coding_xdma.num_threads_prepare 2
```
or
```bash
sudo ./nr-softmodem --sa --rfsim --log_config.global_log_options level,nocolor,time -O ../../../ci-scripts/conf_files/gnb.sa.band78.106prb.rfsim.conf
```
if you have added the configuration to the `.conf` file.
## UE
Example command using rfsim:
```bash
cd ~/openairinterface5g/cmake_targets/ran_build/build
sudo ./nr-uesoftmodem --sa --rfsim -r 106 --numerology 1 --band 78 -C 3319680000 --ue-nb-ant-tx 1 --ue-nb-ant-rx 1 -O ../../../ci-scripts/conf_files/nrue1.uicc.cluCN.conf --rfsimulator.serveraddr 10.201.1.100 --loader.ldpc.shlibversion _xdma --nrLDPC_coding_xdma.num_threads_prepare 2
```
or
```bash
sudo ./nr-uesoftmodem --sa --rfsim -r 106 --numerology 1 --band 78 -C 3319680000 --ue-nb-ant-tx 1 --ue-nb-ant-rx 1 -O ../../../ci-scripts/conf_files/nrue1.uicc.cluCN.conf --rfsimulator.serveraddr 10.201.1.100
```
if you have added the configuration to the `.conf` file.

View File

@@ -35,7 +35,7 @@ This document describes the minimal and performant system requirements for OpenA
|-----------------|
|Ubuntu 20/22/24 |
|RHEL 9 |
|Fedora 40 |
|Fedora 41 |
|Debian 11 |
|Rocky 9 |

View File

@@ -1095,7 +1095,7 @@ void init_transport(PHY_VARS_eNB *eNB) {
exit(-1);
} else {
eNB->dlsch[i][j]->rnti=0;
LOG_D(PHY,"dlsch[%d][%d] => %p rnti:%d\n",i,j,eNB->dlsch[i][j], eNB->dlsch[i][j]->rnti);
LOG_D(PHY, "dlsch[%d][%d] => %p rnti:%x\n", i, j, eNB->dlsch[i][j], eNB->dlsch[i][j]->rnti);
}
}
}

View File

@@ -363,7 +363,6 @@ void wait_RUs(void) {
}
pthread_mutex_unlock(&RC.ru_mutex);
LOG_I(PHY,"RUs configured\n");
}
void wait_eNBs(void) {

View File

@@ -1699,12 +1699,13 @@ void write_dummy(PHY_VARS_UE *UE, openair0_timestamp timestamp) {
for ( int i=0; i < UE->frame_parms.nb_antennas_tx; i++)
samplesVoid[i]=(void *)&v;
AssertFatal( 1 == UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp+2*UE->frame_parms.samples_per_tti,
samplesVoid,
1,
UE->frame_parms.nb_antennas_tx,
1),"");
int written = UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp + 2 * UE->frame_parms.samples_per_tti,
samplesVoid,
1,
UE->frame_parms.nb_antennas_tx,
TX_BURST_START_AND_END);
AssertFatal(1 == written, "write to SDR failed\n");
}
void *UE_thread(void *arg) {

View File

@@ -400,12 +400,12 @@ void term_gNB_Tpool(int inst) {
void init_eNB_afterRU(void) {
int inst,ru_id,i,aa;
PHY_VARS_gNB *gNB;
LOG_I(PHY,"%s() RC.nb_nr_inst:%d\n", __FUNCTION__, RC.nb_nr_inst);
LOG_D(PHY, "%s() RC.nb_nr_inst:%d\n", __FUNCTION__, RC.nb_nr_inst);
if(NFAPI_MODE == NFAPI_MODE_PNF)
RC.nb_nr_inst = 1;
for (inst=0; inst<RC.nb_nr_inst; inst++) {
LOG_I(PHY,"RC.nb_nr_CC[inst:%d]:%p\n", inst, RC.gNB[inst]);
LOG_D(PHY, "RC.nb_nr_CC[inst:%d]:%p\n", inst, RC.gNB[inst]);
gNB = RC.gNB[inst];
gNB->ldpc_offload_flag = get_softmodem_params()->ldpc_offload_flag;
@@ -415,8 +415,7 @@ void init_eNB_afterRU(void) {
// map antennas and PRACH signals to gNB RX
if (0) AssertFatal(gNB->num_RU>0,"Number of RU attached to gNB %d is zero\n",gNB->Mod_id);
LOG_I(PHY,"Mapping RX ports from %d RUs to gNB %d\n",gNB->num_RU,gNB->Mod_id);
LOG_I(PHY,"gNB->num_RU:%d\n", gNB->num_RU);
LOG_D(PHY, "Mapping RX ports from %d RUs to gNB %d\n", gNB->num_RU, gNB->Mod_id);
for (ru_id=0,aa=0; ru_id<gNB->num_RU; ru_id++) {
AssertFatal(gNB->RU_list[ru_id]->common.rxdataF != NULL, "RU %d : common.rxdataF is NULL\n", gNB->RU_list[ru_id]->idx);
@@ -447,30 +446,25 @@ void init_gNB(int wait_for_sync) {
if (RC.gNB == NULL) {
RC.gNB = (PHY_VARS_gNB **) calloc(1+RC.nb_nr_L1_inst, sizeof(PHY_VARS_gNB *));
LOG_I(PHY,"gNB L1 structure RC.gNB allocated @ %p\n",RC.gNB);
LOG_D(PHY, "gNB L1 structure RC.gNB allocated @ %p\n", RC.gNB);
}
for (inst=0; inst<RC.nb_nr_L1_inst; inst++) {
if (RC.gNB[inst] == NULL) {
RC.gNB[inst] = (PHY_VARS_gNB *) calloc(1, sizeof(PHY_VARS_gNB));
LOG_I(PHY,"[nr-gnb.c] gNB structure RC.gNB[%d] allocated @ %p\n",inst,RC.gNB[inst]);
LOG_D(PHY, "[nr-gnb.c] gNB structure RC.gNB[%d] allocated @ %p\n", inst, RC.gNB[inst]);
}
gNB = RC.gNB[inst];
/*nr_polar_init(&gNB->nrPolar_params,
NR_POLAR_PBCH_MESSAGE_TYPE,
NR_POLAR_PBCH_PAYLOAD_BITS,
NR_POLAR_PBCH_AGGREGATION_LEVEL);*/
LOG_I(PHY,"Initializing gNB %d\n",inst);
LOG_I(PHY,"Initializing gNB %d\n",inst);
LOG_I(PHY,"Registering with MAC interface module (before %p)\n",gNB->if_inst);
AssertFatal((gNB->if_inst = NR_IF_Module_init(inst))!=NULL,"Cannot register interface");
LOG_I(PHY,"Registering with MAC interface module (after %p)\n",gNB->if_inst);
AssertFatal((gNB->if_inst = NR_IF_Module_init(inst)) != NULL, "Cannot register interface");
gNB->if_inst->NR_Schedule_response = nr_schedule_response;
gNB->if_inst->NR_PHY_config_req = nr_phy_config_request;
memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO));
LOG_I(PHY,"Setting indication lists\n");
memset(&gNB->UL_INFO, 0, sizeof(gNB->UL_INFO));
gNB->UL_INFO.rx_ind.pdu_list = gNB->rx_pdu_list;
gNB->UL_INFO.crc_ind.crc_list = gNB->crc_pdu_list;
@@ -482,11 +476,7 @@ void init_gNB(int wait_for_sync) {
gNB->prach_energy_counter = 0;
gNB->chest_time = get_softmodem_params()->chest_time;
gNB->chest_freq = get_softmodem_params()->chest_freq;
}
LOG_I(PHY,"[nr-gnb.c] gNB structure allocated\n");
}

View File

@@ -88,7 +88,7 @@ int attach_rru(RU_t *ru) {
memset((void *)&rru_config_msg,0,sizeof(rru_config_msg));
rru_config_msg.type = RAU_tick;
rru_config_msg.len = sizeof(RRU_CONFIG_msg_t)-MAX_RRU_CONFIG_SIZE;
LOG_I(PHY,"Sending RAU tick to RRU %d\n",ru->idx);
LOG_D(PHY, "Sending RAU tick to RRU %d\n", ru->idx);
AssertFatal((ru->ifdevice.trx_ctlsend_func(&ru->ifdevice,&rru_config_msg,rru_config_msg.len)!=-1),
"RU %d cannot access remote radio\n",ru->idx);
msg_len = sizeof(RRU_CONFIG_msg_t)-MAX_RRU_CONFIG_SIZE+sizeof(RRU_capabilities_t);
@@ -97,7 +97,7 @@ int attach_rru(RU_t *ru) {
if ((len = ru->ifdevice.trx_ctlrecv_func(&ru->ifdevice,
&rru_config_msg,
msg_len))<0) {
LOG_I(PHY,"Waiting for RRU %d\n",ru->idx);
LOG_D(PHY, "Waiting for RRU %d\n", ru->idx);
} else if (rru_config_msg.type == RRU_capabilities) {
AssertFatal(rru_config_msg.len==msg_len,"Received capabilities with incorrect length (%d!=%d)\n",(int)rru_config_msg.len,(int)msg_len);
LOG_I(PHY,"Received capabilities from RRU %d (len %d/%d, num_bands %d,max_pdschReferenceSignalPower %d, max_rxgain %d, nb_tx %d, nb_rx %d)\n",ru->idx,
@@ -467,8 +467,7 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) {
RU_proc_t *proc = &ru->proc;
int tti_tx,frame_tx;
openair0_timestamp timestamp_tx = 0;
AssertFatal(1==0,"Shouldn't get here\n");
// printf("Received subframe %d (TS %llu) from RCC\n",tti_tx,timestamp_tx);
AssertFatal(1 == 0, "Shouldn't get here\n");
frame_tx = (timestamp_tx / (fp->samples_per_subframe*10))&1023;
uint32_t idx_sf = timestamp_tx / fp->samples_per_subframe;
tti_tx = (idx_sf * fp->slots_per_subframe + (int)round((float)(timestamp_tx % fp->samples_per_subframe) / fp->samples_per_slot0))%(fp->slots_per_frame);
@@ -693,7 +692,6 @@ static void rx_rf(RU_t *ru, int *frame, int *slot)
*slot = proc->tti_rx;
}
//printf("timestamp_rx %lu, frame %d(%d), subframe %d(%d)\n",ru->timestamp_rx,proc->frame_rx,frame,proc->tti_rx,subframe);
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TS, (proc->timestamp_rx+ru->ts_offset)&0xffffffff );
if (rxs != samples_per_slot) {
@@ -954,9 +952,7 @@ int setup_RU_buffers(RU_t *ru) {
if (ru) {
fp = ru->nr_frame_parms;
printf("setup_RU_buffers: frame_parms = %p\n",fp);
} else {
printf("ru pointer is NULL\n");
return(-1);
}
@@ -973,13 +969,11 @@ int setup_RU_buffers(RU_t *ru) {
for (i=0; i<ru->nb_rx; i++) {
card = i/4;
ant = i%4;
printf("Mapping RU id %u, rx_ant %d, on card %d, chain %d\n",ru->idx,i,ru->rf_map.card+card, ru->rf_map.chain+ant);
LOG_D(PHY, "Mapping RU id %u, rx_ant %d, on card %d, chain %d\n", ru->idx, i, ru->rf_map.card + card, ru->rf_map.chain + ant);
free(ru->common.rxdata[i]);
ru->common.rxdata[i] = ru->openair0_cfg.rxbase[ru->rf_map.chain+ant];
printf("rxdata[%d] @ %p\n",i,ru->common.rxdata[i]);
ru->common.rxdata[i] = ru->openair0_cfg.rxbase[ru->rf_map.chain + ant];
for (j=0; j<16; j++) {
printf("rxbuffer %d: %x\n",j,ru->common.rxdata[i][j]);
for (j = 0; j < 16; j++) {
ru->common.rxdata[i][j] = 16-j;
}
}
@@ -987,13 +981,11 @@ int setup_RU_buffers(RU_t *ru) {
for (i=0; i<ru->nb_tx; i++) {
card = i/4;
ant = i%4;
printf("Mapping RU id %u, tx_ant %d, on card %d, chain %d\n",ru->idx,i,ru->rf_map.card+card, ru->rf_map.chain+ant);
LOG_D(PHY, "Mapping RU id %u, tx_ant %d, on card %d, chain %d\n", ru->idx, i, ru->rf_map.card + card, ru->rf_map.chain + ant);
free(ru->common.txdata[i]);
ru->common.txdata[i] = ru->openair0_cfg.txbase[ru->rf_map.chain+ant];
printf("txdata[%d] @ %p\n",i,ru->common.txdata[i]);
ru->common.txdata[i] = ru->openair0_cfg.txbase[ru->rf_map.chain + ant];
for (j=0; j<16; j++) {
printf("txbuffer %d: %x\n",j,ru->common.txdata[i][j]);
for (j = 0; j < 16; j++) {
ru->common.txdata[i][j] = 16-j;
}
}
@@ -1186,7 +1178,7 @@ void *ru_thread(void *param)
}
if (setup_RU_buffers(ru)!=0) {
printf("Exiting, cannot initialize RU Buffers\n");
LOG_E(PHY, "Exiting, cannot initialize RU Buffers\n");
exit(-1);
}
@@ -1382,8 +1374,6 @@ void *ru_thread(void *param)
pushNotifiedFIFO(&gNB->L1_tx_out, resTx);
}
printf( "Exiting ru_thread \n");
ru_thread_status = 0;
return &ru_thread_status;
}
@@ -1662,18 +1652,15 @@ void set_function_spec_param(RU_t *ru)
ru->start_rf = start_rf; // need to start the local RF interface
ru->stop_rf = stop_rf;
ru->start_write_thread = start_write_thread; // starting RF TX in different thread
printf("configuring ru_id %u (start_rf %p)\n", ru->idx, start_rf);
}
/*
printf("configuring ru_id %u (start_rf %p)\n", ru->idx, start_rf);
fill_rf_config(ru,rf_config_file);
init_frame_parms(&ru->frame_parms,1);
nr_phy_init_RU(ru);
ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg);
if (setup_RU_buffers(ru)!=0) {
printf("Exiting, cannot initialize RU Buffers\n");
exit(-1);
}
*/
@@ -1736,7 +1723,6 @@ void init_NR_RU(configmodule_interface_t *cfg, char *rf_config_file)
pthread_mutex_init(&RC.ru_mutex,NULL);
pthread_cond_init(&RC.ru_cond,NULL);
// read in configuration file)
printf("configuring RU from file\n");
NRRCconfig_RU(cfg);
LOG_I(PHY,"number of L1 instances %d, number of RU %d, number of CPU cores %d\n",RC.nb_nr_L1_inst,RC.nb_RU,get_nprocs());
LOG_D(PHY,"Process RUs RC.nb_RU:%d\n",RC.nb_RU);
@@ -1770,7 +1756,7 @@ void init_NR_RU(configmodule_interface_t *cfg, char *rf_config_file)
AssertFatal(gNB0, "gNB0 is null!\n");
if (gNB0 && gNB_RC) {
LOG_I(PHY,"Copying frame parms from gNB in RC to gNB %d in ru %d and frame_parms in ru\n", gNB0->Mod_id, ru->idx);
LOG_D(PHY, "Copying frame parms from gNB in RC to gNB %d in ru %d and frame_parms in ru\n", gNB0->Mod_id, ru->idx);
memcpy((void *)fp, &gNB_RC->frame_parms, sizeof(NR_DL_FRAME_PARMS));
memcpy((void *)&gNB0->frame_parms, (void *)&gNB_RC->frame_parms, sizeof(NR_DL_FRAME_PARMS));
// attach all RU to all gNBs in its list/
@@ -1786,14 +1772,14 @@ void init_NR_RU(configmodule_interface_t *cfg, char *rf_config_file)
init_RU_proc(ru);
if (ru->if_south != REMOTE_IF4p5) {
int threadCnt = ru->num_tpcores;
if (threadCnt < 2) LOG_E(PHY,"Number of threads for gNB should be more than 1. Allocated only %d\n",threadCnt);
else LOG_I(PHY,"RU Thread pool size %d\n",threadCnt);
if (threadCnt < 2)
LOG_E(PHY, "Number of threads for gNB should be more than 1. Allocated only %d\n", threadCnt);
char pool[80];
int s_offset = sprintf(pool,"%d",ru->tpcores[0]);
for (int icpu=1; icpu<threadCnt; icpu++) {
s_offset+=sprintf(pool+s_offset,",%d",ru->tpcores[icpu]);
}
LOG_I(PHY,"RU thread-pool core string %s\n",pool);
LOG_I(PHY, "RU thread-pool core string %s (size %d)\n", pool, threadCnt);
ru->threadPool = (tpool_t*)malloc(sizeof(tpool_t));
initTpool(pool, ru->threadPool, cpumeas(CPUMEAS_GETSTATE));
// FEP RX result FIFO
@@ -1834,14 +1820,12 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
if (RUParamList.numelt > 0) {
RC.ru = (RU_t **)malloc(RC.nb_RU*sizeof(RU_t *));
RC.ru_mask = (1 << NB_RU) - 1;
printf("Set RU mask to %lx\n",RC.ru_mask);
for (int j = 0; j < RC.nb_RU; j++) {
RC.ru[j] = calloc(1, sizeof(*RC.ru[j]));
RC.ru[j]->idx = j;
RC.ru[j]->nr_frame_parms = calloc(1, sizeof(*RC.ru[j]->nr_frame_parms));
RC.ru[j]->frame_parms = calloc(1, sizeof(*RC.ru[j]->frame_parms));
printf("Creating RC.ru[%d]:%p\n", j, RC.ru[j]);
RC.ru[j]->if_timing = synch_to_ext_device;
if (RC.nb_nr_L1_inst > 0)
@@ -1895,7 +1879,7 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
LOG_E(PHY, "Erroneous RU clock source in the provided configuration file: '%s'\n", *(RUParamList.paramarray[j][RU_SDR_CLK_SRC].strptr));
}
} else {
LOG_I(PHY,"Setting clock source to internal\n");
LOG_D(PHY, "Setting clock source to internal\n");
RC.ru[j]->openair0_cfg.clock_source = internal;
}
@@ -1913,7 +1897,7 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
LOG_E(PHY, "Erroneous RU time source in the provided configuration file: '%s'\n", *(RUParamList.paramarray[j][RU_SDR_CLK_SRC].strptr));
}
} else {
LOG_I(PHY,"Setting time source to internal\n");
LOG_D(PHY, "Setting time source to internal\n");
RC.ru[j]->openair0_cfg.time_source = internal;
}
@@ -1923,7 +1907,7 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
if (!(config_isparamset(RUParamList.paramarray[j],RU_LOCAL_IF_NAME_IDX))) {
RC.ru[j]->if_south = LOCAL_RF;
RC.ru[j]->function = gNodeB_3GPP;
printf("Setting function for RU %d to gNodeB_3GPP\n",j);
LOG_D(PHY, "Setting function for RU %d to gNodeB_3GPP\n", j);
} else {
RC.ru[j]->eth_params.local_if_name = strdup(*(RUParamList.paramarray[j][RU_LOCAL_IF_NAME_IDX].strptr));
RC.ru[j]->eth_params.my_addr = strdup(*(RUParamList.paramarray[j][RU_LOCAL_ADDRESS_IDX].strptr));
@@ -1937,22 +1921,22 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
RC.ru[j]->if_south = LOCAL_RF;
RC.ru[j]->function = NGFI_RRU_IF5;
RC.ru[j]->eth_params.transp_preference = ETH_UDP_MODE;
printf("Setting function for RU %d to NGFI_RRU_IF5 (udp)\n",j);
LOG_D(PHY, "Setting function for RU %d to NGFI_RRU_IF5 (udp)\n", j);
} else if (strcmp(*(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr), "raw") == 0) {
RC.ru[j]->if_south = LOCAL_RF;
RC.ru[j]->function = NGFI_RRU_IF5;
RC.ru[j]->eth_params.transp_preference = ETH_RAW_MODE;
printf("Setting function for RU %d to NGFI_RRU_IF5 (raw)\n",j);
LOG_D(PHY, "Setting function for RU %d to NGFI_RRU_IF5 (raw)\n", j);
} else if (strcmp(*(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr), "udp_if4p5") == 0) {
RC.ru[j]->if_south = LOCAL_RF;
RC.ru[j]->function = NGFI_RRU_IF4p5;
RC.ru[j]->eth_params.transp_preference = ETH_UDP_IF4p5_MODE;
printf("Setting function for RU %d to NGFI_RRU_IF4p5 (udp)\n",j);
LOG_D(PHY, "Setting function for RU %d to NGFI_RRU_IF4p5 (udp)\n", j);
} else if (strcmp(*(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr), "raw_if4p5") == 0) {
RC.ru[j]->if_south = LOCAL_RF;
RC.ru[j]->function = NGFI_RRU_IF4p5;
RC.ru[j]->eth_params.transp_preference = ETH_RAW_IF4p5_MODE;
printf("Setting function for RU %d to NGFI_RRU_IF4p5 (raw)\n",j);
LOG_D(PHY, "Setting function for RU %d to NGFI_RRU_IF4p5 (raw)\n", j);
}
}
@@ -1961,7 +1945,7 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
RC.ru[j]->sf_extension = *(RUParamList.paramarray[j][RU_SF_EXTENSION_IDX].uptr);
} //strcmp(local_rf, "yes") == 0
else {
printf("RU %d: Transport %s\n",j,*(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr));
LOG_D(PHY, "RU %d: Transport %s\n", j, *(RUParamList.paramarray[j][RU_TRANSPORT_PREFERENCE_IDX].strptr));
RC.ru[j]->eth_params.local_if_name = strdup(*(RUParamList.paramarray[j][RU_LOCAL_IF_NAME_IDX].strptr));
RC.ru[j]->eth_params.my_addr = strdup(*(RUParamList.paramarray[j][RU_LOCAL_ADDRESS_IDX].strptr));
RC.ru[j]->eth_params.remote_addr = strdup(*(RUParamList.paramarray[j][RU_REMOTE_ADDRESS_IDX].strptr));
@@ -2006,13 +1990,18 @@ static void NRRCconfig_RU(configmodule_interface_t *cfg)
RC.ru[j]->openair0_cfg.nr_flag = *(RUParamList.paramarray[j][RU_NR_FLAG].iptr);
RC.ru[j]->openair0_cfg.nr_band = RC.ru[j]->band[0];
RC.ru[j]->openair0_cfg.nr_scs_for_raster = *(RUParamList.paramarray[j][RU_NR_SCS_FOR_RASTER].iptr);
printf("[RU %d] Setting nr_flag %d, nr_band %d, nr_scs_for_raster %d\n",j,RC.ru[j]->openair0_cfg.nr_flag,RC.ru[j]->openair0_cfg.nr_band,RC.ru[j]->openair0_cfg.nr_scs_for_raster);
LOG_D(PHY,
"[RU %d] Setting nr_flag %d, nr_band %d, nr_scs_for_raster %d\n",
j,
RC.ru[j]->openair0_cfg.nr_flag,
RC.ru[j]->openair0_cfg.nr_band,
RC.ru[j]->openair0_cfg.nr_scs_for_raster);
RC.ru[j]->openair0_cfg.rxfh_cores[0] = *(RUParamList.paramarray[j][RU_RXFH_CORE_ID].iptr);
RC.ru[j]->openair0_cfg.txfh_cores[0] = *(RUParamList.paramarray[j][RU_TXFH_CORE_ID].iptr);
RC.ru[j]->num_tpcores = *(RUParamList.paramarray[j][RU_NUM_TP_CORES].iptr);
RC.ru[j]->half_slot_parallelization = *(RUParamList.paramarray[j][RU_HALF_SLOT_PARALLELIZATION].iptr);
RC.ru[j]->ru_thread_core = *(RUParamList.paramarray[j][RU_RU_THREAD_CORE].iptr);
printf("[RU %d] Setting half-slot parallelization to %d\n",j,RC.ru[j]->half_slot_parallelization);
LOG_D(PHY, "[RU %d] Setting half-slot parallelization to %d\n", j, RC.ru[j]->half_slot_parallelization);
AssertFatal(RC.ru[j]->num_tpcores <= RUParamList.paramarray[j][RU_TP_CORES].numelt, "Number of TP cores should be <=16\n");
for (int i = 0; i < RC.ru[j]->num_tpcores; i++)
RC.ru[j]->tpcores[i] = RUParamList.paramarray[j][RU_TP_CORES].iptr[i];

View File

@@ -182,12 +182,9 @@ struct timespec clock_difftime(struct timespec start, struct timespec end) {
return temp;
}
void print_difftimes(void) {
#ifdef DEBUG
printf("difftimes min = %lu ns ; max = %lu ns\n", min_diff_time.tv_nsec, max_diff_time.tv_nsec);
#else
LOG_I(HW,"difftimes min = %lu ns ; max = %lu ns\n", min_diff_time.tv_nsec, max_diff_time.tv_nsec);
#endif
void print_difftimes(void)
{
LOG_I(HW, "difftimes min = %lu ns ; max = %lu ns\n", min_diff_time.tv_nsec, max_diff_time.tv_nsec);
}
void update_difftimes(struct timespec start, struct timespec end) {
@@ -268,7 +265,7 @@ static int create_gNB_tasks(ngran_node_t node_type, configmodule_interface_t *cf
uint32_t gnb_id_end = gnb_id_start + gnb_nb;
LOG_D(GNB_APP, "%s(gnb_nb:%d)\n", __FUNCTION__, gnb_nb);
itti_wait_ready(1);
LOG_I(PHY, "%s() Task ready initialize structures\n", __FUNCTION__);
LOG_D(PHY, "%s() Task ready initialize structures\n", __FUNCTION__);
#ifdef ENABLE_AERIAL
AssertFatal(NFAPI_MODE == NFAPI_MODE_AERIAL,"Can only be run with '--nfapi AERIAL' when compiled with AERIAL support, if you want to run other (n)FAPI modes, please run ./build_oai without -w AERIAL");
@@ -283,7 +280,7 @@ static int create_gNB_tasks(ngran_node_t node_type, configmodule_interface_t *cf
if (RC.nb_nr_macrlc_inst > 0)
RCconfig_nr_macrlc(cfg);
LOG_I(PHY, "%s() RC.nb_nr_L1_inst:%d\n", __FUNCTION__, RC.nb_nr_L1_inst);
LOG_D(PHY, "%s() RC.nb_nr_L1_inst:%d\n", __FUNCTION__, RC.nb_nr_L1_inst);
if (RC.nb_nr_L1_inst>0) AssertFatal(l1_north_init_gNB()==0,"could not initialize L1 north interface\n");
@@ -291,7 +288,7 @@ static int create_gNB_tasks(ngran_node_t node_type, configmodule_interface_t *cf
"Number of gNB is greater than gNB defined in configuration file (%d/%d)!",
gnb_nb, RC.nb_nr_inst);
LOG_I(GNB_APP,"Allocating gNB_RRC_INST for %d instances\n",RC.nb_nr_inst);
LOG_D(GNB_APP, "Allocating gNB_RRC_INST for %d instances\n", RC.nb_nr_inst);
if (RC.nb_nr_inst > 0) {
AssertFatal(RC.nb_nr_inst == 1, "multiple RRC instances are not supported\n");
@@ -411,7 +408,6 @@ static void get_options(configmodule_interface_t *cfg)
NRRCConfig();
NB_gNB_INST = RC.nb_nr_inst;
NB_RU = RC.nb_RU;
printf("Configuration: nb_rrc_inst %d, nb_nr_L1_inst %d, nb_ru %hhu\n",NB_gNB_INST,RC.nb_nr_L1_inst,NB_RU);
}
}
@@ -461,24 +457,22 @@ void set_default_frame_parms(nfapi_nr_config_request_scf_t *config[MAX_NUM_CCs],
// downlink_frequency[CC_id][1] = downlink_frequency[CC_id][0];
// downlink_frequency[CC_id][2] = downlink_frequency[CC_id][0];
// downlink_frequency[CC_id][3] = downlink_frequency[CC_id][0];
//printf("Downlink for CC_id %d frequency set to %u\n", CC_id, downlink_frequency[CC_id][0]);
frame_parms[CC_id]->dl_CarrierFreq=downlink_frequency[CC_id][0];
*/
}
}
void wait_RUs(void) {
LOG_I(PHY,"Waiting for RUs to be configured ... RC.ru_mask:%02lx\n", RC.ru_mask);
LOG_D(PHY, "Waiting for RUs to be configured ... RC.ru_mask:%02lx\n", RC.ru_mask);
// wait for all RUs to be configured over fronthaul
pthread_mutex_lock(&RC.ru_mutex);
while (RC.ru_mask>0) {
pthread_cond_wait(&RC.ru_cond,&RC.ru_mutex);
printf("RC.ru_mask:%02lx\n", RC.ru_mask);
}
pthread_mutex_unlock(&RC.ru_mutex);
LOG_I(PHY,"RUs configured\n");
LOG_D(PHY, "RUs configured\n");
}
void wait_gNBs(void) {
@@ -486,7 +480,7 @@ void wait_gNBs(void) {
int waiting=1;
while (waiting==1) {
printf("Waiting for gNB L1 instances to all get configured ... sleeping 50ms (nb_nr_sL1_inst %d)\n",RC.nb_nr_L1_inst);
LOG_D(GNB_APP, "Waiting for gNB L1 instances to all get configured ... sleeping 50ms (nb_nr_sL1_inst %d)\n", RC.nb_nr_L1_inst);
usleep(50*1000);
waiting=0;
@@ -498,7 +492,7 @@ void wait_gNBs(void) {
}
}
printf("gNB L1 are configured\n");
LOG_D(GNB_APP, "gNB L1 are configured\n");
}
/*
@@ -514,15 +508,14 @@ void terminate_task(task_id_t task_id, module_id_t mod_id) {
//extern void free_transport(PHY_VARS_gNB *);
extern void nr_phy_free_RU(RU_t *);
static void wait_nfapi_init(char *thread_name) {
printf( "waiting for NFAPI PNF connection and population of global structure (%s)\n",thread_name);
static void wait_nfapi_init(char *thread_name)
{
pthread_mutex_lock( &nfapi_sync_mutex );
while (nfapi_sync_var<0)
pthread_cond_wait( &nfapi_sync_cond, &nfapi_sync_mutex );
pthread_mutex_unlock(&nfapi_sync_mutex);
printf( "NFAPI: got sync (%s)\n", thread_name);
}
void init_pdcp(void) {
@@ -601,7 +594,6 @@ int main( int argc, char **argv ) {
memset(tx_max_power,0,sizeof(int)*MAX_NUM_CCs);
logInit();
lock_memory_to_ram();
printf("Reading in command-line options\n");
get_options(uniqCfg);
EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1;
@@ -626,7 +618,6 @@ int main( int argc, char **argv ) {
#endif
//randominit (0);
set_taus_seed (0);
printf("configuring for RAU/RRU\n");
cpuf=get_cpu_freq_GHz();
itti_init(TASK_MAX, tasks_info);
@@ -653,27 +644,20 @@ int main( int argc, char **argv ) {
usleep(1000);
if (NFAPI_MODE && NFAPI_MODE != NFAPI_MODE_AERIAL) {
printf("NFAPI*** - mutex and cond created - will block shortly for completion of PNF connection\n");
pthread_cond_init(&sync_cond,NULL);
pthread_mutex_init(&sync_mutex, NULL);
}
printf("START MAIN THREADS\n");
// start the main threads
number_of_cards = 1;
printf("RC.nb_nr_L1_inst:%d\n", RC.nb_nr_L1_inst);
if (RC.nb_nr_L1_inst > 0) {
printf("Initializing gNB threads wait_for_sync:%d\n", wait_for_sync);
init_gNB(wait_for_sync);
}
printf("wait_gNBs()\n");
wait_gNBs();
printf("About to Init RU threads RC.nb_RU:%d\n", RC.nb_RU);
int sl_ahead = NFAPI_MODE == NFAPI_MODE_AERIAL ? 0 : 6;
if (RC.nb_RU >0) {
printf("Initializing RU threads\n");
init_NR_RU(uniqCfg, get_softmodem_params()->rf_config_file);
for (ru_id=0; ru_id<RC.nb_RU; ru_id++) {
@@ -719,12 +703,8 @@ int main( int argc, char **argv ) {
nvIPC_Init(nrmac->nvipc_params_s);
#endif
if (RC.nb_nr_L1_inst > 0) {
printf("wait RUs\n");
wait_RUs();
printf("ALL RUs READY!\n");
printf("RC.nb_RU:%d\n", RC.nb_RU);
// once all RUs are ready initialize the rest of the gNBs ((dependence on final RU parameters after configuration)
printf("ALL RUs ready - init gNBs\n");
for (int idx=0;idx<RC.nb_nr_L1_inst;idx++) RC.gNB[idx]->if_inst->sl_ahead = sl_ahead;
if (IS_SOFTMODEM_DOSCOPE || IS_SOFTMODEM_IMSCOPE_ENABLED) {
@@ -743,15 +723,10 @@ int main( int argc, char **argv ) {
}
if (NFAPI_MODE != NFAPI_MODE_PNF && NFAPI_MODE != NFAPI_MODE_VNF && NFAPI_MODE != NFAPI_MODE_AERIAL) {
printf("Not NFAPI mode - call init_eNB_afterRU()\n");
init_eNB_afterRU();
} else {
printf("NFAPI mode - DO NOT call init_gNB_afterRU()\n");
}
printf("ALL RUs ready - ALL gNBs ready\n");
// connect the TX/RX buffers
printf("Sending sync to all threads\n");
pthread_mutex_lock(&sync_mutex);
sync_var=0;
pthread_cond_broadcast(&sync_cond);
@@ -759,12 +734,10 @@ int main( int argc, char **argv ) {
}
// wait for end of program
printf("Entering ITTI signals handler\n");
printf("TYPE <CTRL-C> TO TERMINATE\n");
itti_wait_tasks_end(NULL);
printf("Returned from ITTI signal handler\n");
oai_exit=1;
printf("oai_exit=%d\n",oai_exit);
// cleanup
if (RC.nb_nr_L1_inst > 0)

View File

@@ -43,7 +43,6 @@
//#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all
#include "openair1/PHY/MODULATION/nr_modulation.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
#include "PHY/phy_vars_nr_ue.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
@@ -388,7 +387,6 @@ configmodule_interface_t *uniqCfg = NULL;
// A global var to reduce the changes size
ldpc_interface_t ldpc_interface = {0}, ldpc_interface_offload = {0};
nrLDPC_coding_interface_t nrLDPC_coding_interface = {0};
int main(int argc, char **argv)
{
@@ -425,15 +423,10 @@ int main(int argc, char **argv)
init_opt();
int nrLDPC_coding_interface_flag = 0;
int ret_loader = load_nrLDPC_coding_interface(NULL, &nrLDPC_coding_interface);
if (ret_loader >= 0) {
nrLDPC_coding_interface_flag = 1;
} else {
load_LDPClib(NULL, &ldpc_interface);
if (nrUE_params.ldpc_offload_flag)
load_LDPClib("_t2", &ldpc_interface_offload);
}
if (nrUE_params.ldpc_offload_flag)
load_LDPClib("_t2", &ldpc_interface_offload);
load_LDPClib(NULL, &ldpc_interface);
if (ouput_vcd) {
vcd_signal_dumper_init("/tmp/openair_dump_nrUE.vcd");
@@ -448,7 +441,6 @@ int main(int argc, char **argv)
for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
PHY_vars_UE_g[inst][CC_id] = malloc(sizeof(*PHY_vars_UE_g[inst][CC_id]));
memset(PHY_vars_UE_g[inst][CC_id], 0, sizeof(*PHY_vars_UE_g[inst][CC_id]));
PHY_vars_UE_g[inst][CC_id]->nrLDPC_coding_interface_flag = nrLDPC_coding_interface_flag;
}
}

View File

@@ -47,15 +47,10 @@ const char *nfapi_get_strmode(void) {
return nfapi_str_mode[nfapi_params.nfapi_mode];
}
void nfapi_logmode() {
LOG_I(ENB_APP,"nfapi (%d) running mode: %s\n",nfapi_params.nfapi_mode,nfapi_get_strmode());
}
nfapi_mode_t nfapi_getmode(void) {
return nfapi_params.nfapi_mode;
}
void nfapi_setmode(nfapi_mode_t nfapi_mode) {
nfapi_params.nfapi_mode = nfapi_mode;
nfapi_logmode();
}

View File

@@ -1,4 +1,3 @@
add_subdirectory(nr_phy_common)
add_subdirectory(TOOLS)
add_subdirectory(NR_TRANSPORT)
add_subdirectory(CODING)

View File

@@ -1,3 +0,0 @@
if(ENABLE_TESTS)
add_subdirectory(tests)
endif()

View File

@@ -1,12 +1,7 @@
# LDPC coding implementation
The LDPC encoder and decoder are implemented in a shared library, dynamically loaded at run-time using the [oai shared library loader](file://../../../../common/utils/DOC/loader.md).
Two types of library are available with two different interfaces. There are libraries implementing the encoder and decoder of code segments and libraries implementing the encoder and decoder of slots.
# LDPC coder/decoder implementation
The LDPC coder and decoder are implemented in a shared library, dynamically loaded at run-time using the [oai shared library loader](file://../../../../common/utils/DOC/loader.md). The code loading the LDPC library is in [nrLDPC_load.c](file://../nrLDPC_load.c), in function `load_nrLDPClib`, which must be called at init time.
## LDPC segment coding
The interface of the library is defined in [nrLDPC_defs.h](file://../nrLDPC_defs.h).
The code loading the LDPC library is in [nrLDPC_load.c](file://../nrLDPC_load.c), in function `load_nrLDPClib`, which must be called at init time.
### Selecting the LDPC library at run time
## Selecting the LDPC library at run time
By default the function `int load_nrLDPClib(void)` looks for `libldpc.so`, this default behavior can be changed using the oai loader configuration options in the configuration file or from the command line as shown below:
@@ -123,7 +118,7 @@ At runtime, to successfully use hardware acceleration via OpenCL, you need to in
------------------------------------------------------------
```
A mechanism to select ldpc implementation is also available in the `ldpctest` phy simulator via the `-v` option, which can be used to specify the version of the ldpc shared library to be used.
A mechanism to select ldpc implementation is also available in the `ldpctest` phy simulator via the `-v`option, which can be used to specify the version of the ldpc shared library to be used.
#### Examples of ldpc shared lib selection when running ldpctest:
@@ -201,115 +196,4 @@ Libraries implementing the LDPC algorithms must be named `libldpc<_version>.so`,
`libldpc_cl.so`is under development.
## LDPC slot coding
The interface of the library is defined in [nrLDPC_coding_interface.h](file://../nrLDPC_coding/nrLDPC_coding_interface.h).
The code loading the LDPC library is in [nrLDPC_coding_interface_load.c](file://../nrLDPC_coding/nrLDPC_coding_interface_load.c), in function `load_nrLDPC_coding_interface`, which must be called at init time.
### Selecting the LDPC library at run time
By default the function `int load_nrLDPC_coding_interface(void)` looks for `libldpc.so`.\
If `libldpc.so` does not implement the LDPC slot decoder interface then the loader just fails which allows to fallback to the code segment decoding interface.\
This default behavior can be changed using the oai loader configuration options in the configuration file or from the command line as shown below:
#### Examples of ldpc shared lib selection when running nr softmodem's:
loading `libldpc_slot_segment.so` instead of `libldpc.so`:
```
./nr-softmodem -O libconfig:gnb.band78.tm1.106PRB.usrpx300.conf:dbgl5 --loader.ldpc.shlibversion _slot_segment
.......................
[CONFIG] loader.ldpc.shlibversion set to default value ""
[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value)
[CONFIG] shlibversion set to _slot_segment from command line
[CONFIG] loader.ldpc 1 options set from command line
shlib_path libldpc_slot_segment.so
[LOADER] library libldpc_slot_segment.so successfully loaded
........................
```
`libldpc_slot_segment.so` has its decoder implemented in [nrLDPC_coding_segment_decoder.c](file://../nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_decoder.c).\
Its encoder is implemented in [nrLDPC_coding_segment_encoder.c](file://../nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c).
*Note: `libldpc_slot_segment.so` is just to test the slot coding interface and uses a segment coding library behind.*
*The segment coding library is `libldpc.so` by default but it can be chosen with option `--nrLDPC_coding_segment.segment_shlibversion` followed by the library version - like with `--loder.ldpc.shlibversion` in the segment coding case above -*
loading `libldpc_slot_t2.so` instead of `libldpc.so`:
`make ldpc_slot_t2`
This command creates the `libldpc_slot_t2.so` shared library.
```
Building C object CMakeFiles/ldpc_slot_t2.dir/openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_t2/nrLDPC_coding_t2.c.o
Linking C shared module libldpc_slot_t2.so
```
At runtime, to successfully use the T2 board, you need to install vendor specific drivers and tools.\
Please refer to the dedicated documentation at [LDPC_T2_OFFLOAD_SETUP.md](file://../../../../doc/LDPC_T2_OFFLOAD_SETUP.md).
`./nr-softmodem -O libconfig:gnb.band78.sa.fr1.106PRB.usrpb210.conf:dbgl5 --rfsim --rfsimulator.serveraddr server --sa --log_config.gtpu_log_level info --loader.ldpc.shlibversion _slot_t2 --nrLDPC_coding_t2.dpdk_dev 01:00.0 --nrLDPC_coding_t2.dpdk_core_list 0-1`
```
.......................
[CONFIG] loader.ldpc.shlibversion set to default value ""
[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value)
[CONFIG] shlibversion set to _slot_t2 from command line
[CONFIG] loader.ldpc 1 options set from command line
shlib_path libldpc_slot_t2.so
[LOADER] library libldpc_slot_t2.so successfully loaded
........................
```
`libldpc_slot_t2.so` has its decoder and its encoder implemented in [nrLDPC_coding_t2.c](file://../nrLDPC_coding/nrLDPC_coding_t2/nrLDPC_coding_t2.c).
loading `libldpc_xdma.so` instead of `libldpc.so`:
`make ldpc_xdma` or `ninja ldpc_xdma`
This command creates the `libldpc_xdma.so` shared library.
```
ninja ldpc_xdma
[2/2] Linking C shared module libldpc_xdma.so
```
At runtime, to successfully use the xdma, you need to install vendor specific drivers and tools.\
Please refer to the dedicated documentation at [LDPC_XDMA_OFFLOAD_SETUP.md](file://../../../../doc/LDPC_XDMA_OFFLOAD_SETUP.md).
`./nr-softmodem -O libconfig:gnb.band78.sa.fr1.106PRB.usrpb210.conf:dbgl5 --rfsim --rfsimulator.serveraddr server --sa --log_config.gtpu_log_level info --loader.ldpc.shlibversion _xdma --nrLDPC_coding_xdma.num_threads_prepare 2`
```
.......................
[CONFIG] loader.ldpc.shlibversion set to default value ""
[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value)
[CONFIG] shlibversion set to _xdma from command line
[CONFIG] loader.ldpc 1 options set from command line
shlib_path libldpc_xdma.so
[LOADER] library libldpc_xdma.so successfully loaded
........................
```
`libldpc_xdma.so` has its decoder implemented in [nrLDPC_coding_xdma.c](file://../nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma.c).\
Its encoder is implemented in [nrLDPC_coding_segment_encoder.c](file://../nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c).
*Note: `libldpc_xdma.so` relies on a segment coding library for encoding.*
*The segment coding library is `libldpc.so` by default but it can be chosen with option `--nrLDPC_coding_xdma.encoder_shlibversion` followed by the library version - like with `--loder.ldpc.shlibversion` in the segment coding case above -*
#### Examples of ldpc shared lib selection when running ldpctest:
Slot coding libraries cannot be used yet within ldpctest.
But they can be used within nr_ulsim, nr_dlsim, nr_ulschsim and nr_dlschsim.\
In these PHY simulators, using the slot coding libraries is enabled in the exact same way as in nr-softmodem.
### LDPC libraries
Libraries implementing the slotwise LDPC coding must be named `libldpc<_version>.so`. They must implement four functions: `nrLDPC_coding_init`, `nrLDPC_coding_shutdown`, `nrLDPC_coding_decoder` and `nrLDPC_coding_encoder`. The prototypes for these functions is defined in [nrLDPC_coding_interface.h](file://../nrLDPC_coding/nrLDPC_coding_interface.h).
`libldpc_slot_segment.so` is completed.
`libldpc_slot_t2.so` is completed.
`libldpc_xdma.so` is completed.
[oai Wikis home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home)

View File

@@ -1,263 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h
* \brief interface for libraries implementing coding/decoding algorithms
*/
#include "PHY/defs_gNB.h"
#ifndef __NRLDPC_CODING_INTERFACE__H__
#define __NRLDPC_CODING_INTERFACE__H__
/**
* \typedef nrLDPC_segment_decoding_parameters_t
* \struct nrLDPC_segment_decoding_parameters_s
* \brief decoding parameter of segments
* \var E input llr segment size
* \var R
* \var llr input llr segment array
* \var d Pointers to code blocks before LDPC decoding (38.212 V15.4.0 section 5.3.2)
* \var d_to_be_cleared
* pointer to the flag used to clear d properly
* when true, clear d after rate dematching
* \var c Pointers to code blocks after LDPC decoding (38.212 V15.4.0 section 5.2.2)
* \var decodeSuccess
* flag indicating that the decoding of the segment was successful
* IT MUST BE FILLED BY THE IMPLEMENTATION
* \var ts_deinterleave deinterleaving time stats
* \var ts_rate_unmatch rate unmatching time stats
* \var ts_ldpc_decode decoding time stats
*/
typedef struct nrLDPC_segment_decoding_parameters_s{
int E;
uint8_t R;
short *llr;
int16_t *d;
bool *d_to_be_cleared;
uint8_t *c;
bool decodeSuccess;
time_stats_t ts_deinterleave;
time_stats_t ts_rate_unmatch;
time_stats_t ts_ldpc_decode;
} nrLDPC_segment_decoding_parameters_t;
/**
* \typedef nrLDPC_TB_decoding_parameters_t
* \struct nrLDPC_TB_decoding_parameters_s
* \brief decoding parameter of transport blocks
* \var xlsch_id ulsch or dlsch index
* \var processedSegments
* pointer to the number of succesfully decoded segments
* it initially holds the total number of segments decoded after the previous HARQ round
* it finally holds the total number of segments decoded after the current HARQ round
* \var rnti RNTI
* \var nb_rb number of resource blocks
* \var Qm modulation order
* \var mcs MCS
* \var nb_layers number of layers
* \var BG LDPC base graph id
* \var rv_index
* \var max_ldpc_iterations maximum number of LDPC iterations
* \var abort_decode pointer to decode abort flag
* \var G
* \var tbslbrm Transport block size LBRM
* \var A Transport block size (This is A from 38.212 V15.4.0 section 5.1)
* \var K
* \var Z lifting size
* \var F filler bits size
* \var C number of segments
* \var segments array of segments parameters
*/
typedef struct nrLDPC_TB_decoding_parameters_s{
uint8_t xlsch_id;
uint32_t *processedSegments;
uint16_t rnti;
uint16_t nb_rb;
uint8_t Qm;
uint8_t mcs;
uint8_t nb_layers;
uint8_t BG;
uint8_t rv_index;
uint8_t max_ldpc_iterations;
decode_abort_t *abort_decode;
uint32_t G;
uint32_t tbslbrm;
uint32_t A;
uint32_t K;
uint32_t Z;
uint32_t F;
uint32_t C;
nrLDPC_segment_decoding_parameters_t *segments;
} nrLDPC_TB_decoding_parameters_t;
/**
* \typedef nrLDPC_slot_decoding_parameters_t
* \struct nrLDPC_slot_decoding_parameters_s
* \brief decoding parameter of slot
* \var frame frame index
* \var slot slot index
* \var nb_TBs number of transport blocks
* \var respDecode pointer to the queue for decoding tasks
* \var threadPool pointer to the thread pool
* \var TBs array of TBs decoding parameters
*/
typedef struct nrLDPC_slot_decoding_parameters_s{
int frame;
int slot;
int nb_TBs;
notifiedFIFO_t *respDecode;
tpool_t *threadPool;
nrLDPC_TB_decoding_parameters_t *TBs;
} nrLDPC_slot_decoding_parameters_t;
/**
* \typedef nrLDPC_segment_encoding_parameters_t
* \struct nrLDPC_segment_encoding_parameters_s
* \brief encoding parameter of segments
* \var E input llr segment size
* \var output input llr segment array
* \var c Pointers to code blocks before LDPC encoding (38.212 V15.4.0 section 5.2.2)
* flag indicating that the decoding of the segment was successful
* IT MUST BE FILLED BY THE IMPLEMENTATION
* \var ts_interleave interleaving time stats
* \var ts_rate_match rate matching time stats
* \var ts_ldpc_encode encoding time stats
*/
typedef struct nrLDPC_segment_encoding_parameters_s{
int E;
unsigned char *output;
uint8_t *c;
time_stats_t ts_interleave;
time_stats_t ts_rate_match;
time_stats_t ts_ldpc_encode;
} nrLDPC_segment_encoding_parameters_t;
/**
* \typedef nrLDPC_TB_encoding_parameters_t
* \struct nrLDPC_TB_encoding_parameters_s
* \brief encoding parameter of transport blocks
* \var xlsch_id ulsch or dlsch index
* \var rnti RNTI
* \var nb_rb number of resource blocks
* \var Qm modulation order
* \var mcs MCS
* \var nb_layers number of layers
* \var BG LDPC base graph id
* \var rv_index
* \var G
* \var tbslbrm Transport block size LBRM
* \var A Transport block size (This is A from 38.212 V15.4.0 section 5.1)
* \var Kb
* \var K
* \var Z lifting size
* \var F filler bits size
* \var C number of segments
* \var segments array of segments parameters
*/
typedef struct nrLDPC_TB_encoding_parameters_s{
uint8_t xlsch_id;
uint16_t rnti;
uint16_t nb_rb;
uint8_t Qm;
uint8_t mcs;
uint8_t nb_layers;
uint8_t BG;
uint8_t rv_index;
uint32_t G;
uint32_t tbslbrm;
uint32_t A;
uint32_t Kb;
uint32_t K;
uint32_t Z;
uint32_t F;
uint32_t C;
nrLDPC_segment_encoding_parameters_t *segments;
} nrLDPC_TB_encoding_parameters_t;
/**
* \typedef nrLDPC_slot_encoding_parameters_t
* \struct nrLDPC_slot_encoding_parameters_s
* \brief encoding parameter of slot
* \var frame frame index
* \var slot slot index
* \var nb_TBs number of transport blocks
* \var respEncode pointer to the queue for encoding tasks
* \var threadPool pointer to the thread pool
* \var tinput pointer to the input timer struct
* \var tprep pointer to the preparation timer struct
* \var tparity pointer to the parity timer struct
* \var toutput pointer to the output timer struct
* \var TBs array of TBs decoding parameters
*/
typedef struct nrLDPC_slot_encoding_parameters_s{
int frame;
int slot;
int nb_TBs;
notifiedFIFO_t *respEncode;
tpool_t *threadPool;
time_stats_t *tinput;
time_stats_t *tprep;
time_stats_t *tparity;
time_stats_t *toutput;
nrLDPC_TB_encoding_parameters_t *TBs;
} nrLDPC_slot_encoding_parameters_t;
typedef int32_t(nrLDPC_coding_init_t)(void);
typedef int32_t(nrLDPC_coding_shutdown_t)(void);
/**
* \brief slot decoding function interface
* \param nrLDPC_slot_decoding_parameters pointer to the structure holding the parameters necessary for decoding
*/
typedef int32_t(nrLDPC_coding_decoder_t)(nrLDPC_slot_decoding_parameters_t *nrLDPC_slot_decoding_parameters);
/**
* \brief slot encoding function interface
* \param nrLDPC_slot_encoding_parameters pointer to the structure holding the parameters necessary for encoding
*/
typedef int32_t(nrLDPC_coding_encoder_t)(nrLDPC_slot_encoding_parameters_t *nrLDPC_slot_encoding_parameters);
typedef struct nrLDPC_coding_interface_s {
nrLDPC_coding_init_t *nrLDPC_coding_init;
nrLDPC_coding_shutdown_t *nrLDPC_coding_shutdown;
nrLDPC_coding_decoder_t *nrLDPC_coding_decoder;
nrLDPC_coding_encoder_t *nrLDPC_coding_encoder;
} nrLDPC_coding_interface_t;
int load_nrLDPC_coding_interface(char *version, nrLDPC_coding_interface_t *interface);
int free_nrLDPC_coding_interface(nrLDPC_coding_interface_t *interface);
//TODO replace the global structure below
// Global var to limit the rework of the dirty legacy code
extern nrLDPC_coding_interface_t nrLDPC_coding_interface;
#endif

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@@ -1,74 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface_load.c
* \brief load library implementing coding/decoding algorithms
*/
#define _GNU_SOURCE
#include <sys/types.h>
#include <stdlib.h>
#include <malloc.h>
#include "assertions.h"
#include "common/utils/LOG/log.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
#include "PHY/CODING/nrLDPC_extern.h"
#include "common/config/config_userapi.h"
#include "common/utils/load_module_shlib.h"
/* arguments used when called from phy simulators exec's which do not use the config module */
/* arg is used to initialize the config module so that the loader works as expected */
char *arguments_phy_simulators[64]={"ldpctest",NULL};
int load_nrLDPC_coding_interface(char *version, nrLDPC_coding_interface_t *itf)
{
char *ptr = (char *)config_get_if();
char libname[64] = "ldpc";
if (ptr == NULL) { // phy simulators, config module possibly not loaded
uniqCfg = load_configmodule(1, arguments_phy_simulators, CONFIG_ENABLECMDLINEONLY);
logInit();
}
/* function description array, to be used when loading the encoding/decoding shared lib */
loader_shlibfunc_t shlib_fdesc[] = {{.fname = "nrLDPC_coding_init"},
{.fname = "nrLDPC_coding_shutdown"},
{.fname = "nrLDPC_coding_decoder"},
{.fname = "nrLDPC_coding_encoder"}};
int ret;
ret = load_module_version_shlib(libname, version, shlib_fdesc, sizeofArray(shlib_fdesc), NULL);
if(ret < 0){
LOG_D(PHY, "NR ULSCH decoding module unavailable");
return ret;
}
itf->nrLDPC_coding_init = (nrLDPC_coding_init_t *)shlib_fdesc[0].fptr;
itf->nrLDPC_coding_shutdown = (nrLDPC_coding_shutdown_t *)shlib_fdesc[1].fptr;
itf->nrLDPC_coding_decoder = (nrLDPC_coding_decoder_t *)shlib_fdesc[2].fptr;
itf->nrLDPC_coding_encoder = (nrLDPC_coding_encoder_t *)shlib_fdesc[3].fptr;
AssertFatal(itf->nrLDPC_coding_init() == 0, "error starting LDPC library %s %s\n", libname, version);
return 0;
}
int free_nrLDPC_coding_interface(nrLDPC_coding_interface_t *interface)
{
return interface->nrLDPC_coding_shutdown();
}

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@@ -1,319 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/CODING/nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_decoder.c
* \brief Top-level routines for decoding LDPC transport channels
*/
// [from gNB coding]
#include "PHY/defs_gNB.h"
#include "PHY/CODING/coding_extern.h"
#include "PHY/CODING/coding_defs.h"
#include "PHY/CODING/lte_interleaver_inline.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
#include "PHY/CODING/nrLDPC_extern.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "SCHED_NR/sched_nr.h"
#include "SCHED_NR/fapi_nr_l1.h"
#include "defs.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "common/utils/LOG/log.h"
#include <syscall.h>
//#define gNB_DEBUG_TRACE
#define OAI_LDPC_DECODER_MAX_NUM_LLR 27000 //26112 // NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX = 68*384
//#define DEBUG_CRC
#ifdef DEBUG_CRC
#define PRINT_CRC_CHECK(a) a
#else
#define PRINT_CRC_CHECK(a)
#endif
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_interface.h"
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h"
/**
* \typedef nrLDPC_decoding_parameters_t
* \struct nrLDPC_decoding_parameters_s
* \brief decoding parameter of transport blocks
* \var decoderParams decoder parameters
* \var Qm modulation order
* \var Kc size of base graph input
* \var rv_index
* \var max_number_iterations maximum number of LDPC iterations
* \var abort_decode pointer to decode abort flag
* \var tbslbrm transport block size LBRM in bytes
* \var A Transport block size (This is A from 38.212 V15.4.0 section 5.1)
* \var K
* \var Z lifting size
* \var F filler bits size
* \var r segment index in TB
* \var E input llr segment size
* \var C number of segments
* \var llr input llr segment array
* \var d Pointers to code blocks before LDPC decoding (38.212 V15.4.0 section 5.3.2)
* \var d_to_be_cleared
* pointer to the flag used to clear d properly
* when true, clear d after rate dematching
* \var c Pointers to code blocks after LDPC decoding (38.212 V15.4.0 section 5.2.2)
* \var decodeSuccess pointer to the flag indicating that the decoding of the segment was successful
* \var p_ts_deinterleave pointer to deinterleaving time stats
* \var p_ts_rate_unmatch pointer to rate unmatching time stats
* \var p_ts_ldpc_decode pointer to decoding time stats
*/
typedef struct nrLDPC_decoding_parameters_s{
t_nrLDPC_dec_params decoderParms;
uint8_t Qm;
uint8_t Kc;
uint8_t rv_index;
decode_abort_t *abort_decode;
uint32_t tbslbrm;
uint32_t A;
uint32_t K;
uint32_t Z;
uint32_t F;
uint32_t C;
int E;
short *llr;
int16_t *d;
bool *d_to_be_cleared;
uint8_t *c;
bool *decodeSuccess;
time_stats_t *p_ts_deinterleave;
time_stats_t *p_ts_rate_unmatch;
time_stats_t *p_ts_ldpc_decode;
} nrLDPC_decoding_parameters_t;
// Global var to limit the rework of the dirty legacy code
ldpc_interface_t ldpc_interface_segment;
static void nr_process_decode_segment(void *arg)
{
nrLDPC_decoding_parameters_t *rdata = (nrLDPC_decoding_parameters_t *)arg;
t_nrLDPC_dec_params *p_decoderParms = &rdata->decoderParms;
const int Kr = rdata->K;
const int Kr_bytes = Kr >> 3;
const int K_bits_F = Kr - rdata->F;
const int A = rdata->A;
const int E = rdata->E;
const int Qm = rdata->Qm;
const int rv_index = rdata->rv_index;
const uint8_t kc = rdata->Kc;
short *ulsch_llr = rdata->llr;
int8_t llrProcBuf[OAI_LDPC_DECODER_MAX_NUM_LLR] __attribute__((aligned(32)));
t_nrLDPC_time_stats procTime = {0};
t_nrLDPC_time_stats *p_procTime = &procTime;
////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// nr_deinterleaving_ldpc ///////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////// ulsch_llr =====> ulsch_harq->e //////////////////////////////
start_meas(rdata->p_ts_deinterleave);
/// code blocks after bit selection in rate matching for LDPC code (38.212 V15.4.0 section 5.4.2.1)
int16_t harq_e[E];
nr_deinterleaving_ldpc(E, Qm, harq_e, ulsch_llr);
//////////////////////////////////////////////////////////////////////////////////////////
stop_meas(rdata->p_ts_deinterleave);
start_meas(rdata->p_ts_rate_unmatch);
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// nr_rate_matching_ldpc_rx ////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////// ulsch_harq->e =====> ulsch_harq->d /////////////////////////
if (nr_rate_matching_ldpc_rx(rdata->tbslbrm,
p_decoderParms->BG,
p_decoderParms->Z,
rdata->d,
harq_e,
rdata->C,
rv_index,
*rdata->d_to_be_cleared,
E,
rdata->F,
Kr - rdata->F - 2 * (p_decoderParms->Z))
== -1) {
stop_meas(rdata->p_ts_rate_unmatch);
LOG_E(PHY, "nrLDPC_coding_segment_decoder.c: Problem in rate_matching\n");
return;
}
stop_meas(rdata->p_ts_rate_unmatch);
*rdata->d_to_be_cleared = false;
memset(rdata->c, 0, Kr_bytes);
p_decoderParms->crc_type = crcType(rdata->C, A);
p_decoderParms->E = lenWithCrc(rdata->C, A);
// set first 2*Z_c bits to zeros
int16_t z[68 * 384 + 16] __attribute__((aligned(16)));
start_meas(rdata->p_ts_ldpc_decode);
memset(z, 0, 2 * rdata->Z * sizeof(*z));
// set Filler bits
memset(z + K_bits_F, 127, rdata->F * sizeof(*z));
// Move coded bits before filler bits
memcpy(z + 2 * rdata->Z, rdata->d, (K_bits_F - 2 * rdata->Z) * sizeof(*z));
// skip filler bits
memcpy(z + Kr, rdata->d + (Kr - 2 * rdata->Z), (kc * rdata->Z - Kr) * sizeof(*z));
// Saturate coded bits before decoding into 8 bits values
simde__m128i *pv = (simde__m128i *)&z;
int8_t l[68 * 384 + 16] __attribute__((aligned(16)));
simde__m128i *pl = (simde__m128i *)&l;
for (int i = 0, j = 0; j < ((kc * rdata->Z) >> 4) + 1; i += 2, j++) {
pl[j] = simde_mm_packs_epi16(pv[i], pv[i + 1]);
}
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// nrLDPC_decoder /////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// pl =====> llrProcBuf //////////////////////////////////
int decodeIterations =
ldpc_interface_segment.LDPCdecoder(p_decoderParms, 0, 0, 0, l, llrProcBuf, p_procTime, rdata->abort_decode);
if (decodeIterations <= p_decoderParms->numMaxIter) {
memcpy(rdata->c,llrProcBuf, Kr>>3);
*rdata->decodeSuccess = true;
} else {
*rdata->decodeSuccess = false;
}
stop_meas(rdata->p_ts_ldpc_decode);
}
int nrLDPC_prepare_TB_decoding(nrLDPC_slot_decoding_parameters_t *nrLDPC_slot_decoding_parameters, int pusch_id)
{
nrLDPC_TB_decoding_parameters_t *nrLDPC_TB_decoding_parameters = &nrLDPC_slot_decoding_parameters->TBs[pusch_id];
*nrLDPC_TB_decoding_parameters->processedSegments = 0;
t_nrLDPC_dec_params decParams = {.check_crc = check_crc};
decParams.BG = nrLDPC_TB_decoding_parameters->BG;
decParams.Z = nrLDPC_TB_decoding_parameters->Z;
decParams.numMaxIter = nrLDPC_TB_decoding_parameters->max_ldpc_iterations;
decParams.outMode = 0;
for (int r = 0; r < nrLDPC_TB_decoding_parameters->C; r++) {
union ldpcReqUnion id = {.s = {nrLDPC_TB_decoding_parameters->rnti, nrLDPC_slot_decoding_parameters->frame, nrLDPC_slot_decoding_parameters->slot, 0, 0}};
notifiedFIFO_elt_t *req = newNotifiedFIFO_elt(sizeof(nrLDPC_decoding_parameters_t), id.p, nrLDPC_slot_decoding_parameters->respDecode, &nr_process_decode_segment);
nrLDPC_decoding_parameters_t *rdata = (nrLDPC_decoding_parameters_t *)NotifiedFifoData(req);
decParams.R = nrLDPC_TB_decoding_parameters->segments[r].R;
decParams.setCombIn = !nrLDPC_TB_decoding_parameters->segments[r].d_to_be_cleared;
rdata->decoderParms = decParams;
rdata->llr = nrLDPC_TB_decoding_parameters->segments[r].llr;
rdata->Kc = decParams.BG == 2 ? 52 : 68;
rdata->C = nrLDPC_TB_decoding_parameters->C;
rdata->E = nrLDPC_TB_decoding_parameters->segments[r].E;
rdata->A = nrLDPC_TB_decoding_parameters->A;
rdata->Qm = nrLDPC_TB_decoding_parameters->Qm;
rdata->K = nrLDPC_TB_decoding_parameters->K;
rdata->Z = nrLDPC_TB_decoding_parameters->Z;
rdata->F = nrLDPC_TB_decoding_parameters->F;
rdata->rv_index = nrLDPC_TB_decoding_parameters->rv_index;
rdata->tbslbrm = nrLDPC_TB_decoding_parameters->tbslbrm;
rdata->abort_decode = nrLDPC_TB_decoding_parameters->abort_decode;
rdata->d = nrLDPC_TB_decoding_parameters->segments[r].d;
rdata->d_to_be_cleared = nrLDPC_TB_decoding_parameters->segments[r].d_to_be_cleared;
rdata->c = nrLDPC_TB_decoding_parameters->segments[r].c;
rdata->decodeSuccess = &nrLDPC_TB_decoding_parameters->segments[r].decodeSuccess;
rdata->p_ts_deinterleave = &nrLDPC_TB_decoding_parameters->segments[r].ts_deinterleave;
rdata->p_ts_rate_unmatch = &nrLDPC_TB_decoding_parameters->segments[r].ts_rate_unmatch;
rdata->p_ts_ldpc_decode = &nrLDPC_TB_decoding_parameters->segments[r].ts_ldpc_decode;
pushTpool(nrLDPC_slot_decoding_parameters->threadPool, req);
LOG_D(PHY, "Added a block to decode, in pipe: %d\n", r);
}
return nrLDPC_TB_decoding_parameters->C;
}
int32_t nrLDPC_coding_init(void){
char *segment_shlibversion = NULL;
paramdef_t LoaderParams[] = {
{"segment_shlibversion", NULL, 0, .strptr = &segment_shlibversion, .defstrval = "", TYPE_STRING, 0, NULL}
};
config_get(config_get_if(), LoaderParams, sizeofArray(LoaderParams), "nrLDPC_coding_segment");
load_LDPClib(segment_shlibversion, &ldpc_interface_segment);
return 0;
}
int32_t nrLDPC_coding_shutdown(void){
free_LDPClib(&ldpc_interface_segment);
return 0;
}
int32_t nrLDPC_coding_decoder(nrLDPC_slot_decoding_parameters_t *nrLDPC_slot_decoding_parameters){
int nbDecode = 0;
for (int pusch_id = 0; pusch_id < nrLDPC_slot_decoding_parameters->nb_TBs; pusch_id++) {
nbDecode += nrLDPC_prepare_TB_decoding(nrLDPC_slot_decoding_parameters, pusch_id);
}
// Execute thread pool tasks if any
while (nbDecode > 0) {
notifiedFIFO_elt_t *req = pullTpool(nrLDPC_slot_decoding_parameters->respDecode, nrLDPC_slot_decoding_parameters->threadPool);
if (req == NULL)
return -1; // Tpool has been stopped
delNotifiedFIFO_elt(req);
nbDecode--;
}
for (int pusch_id = 0; pusch_id < nrLDPC_slot_decoding_parameters->nb_TBs; pusch_id++) {
nrLDPC_TB_decoding_parameters_t *nrLDPC_TB_decoding_parameters = &nrLDPC_slot_decoding_parameters->TBs[pusch_id];
for (int r = 0; r < nrLDPC_TB_decoding_parameters->C; r++) {
if (nrLDPC_TB_decoding_parameters->segments[r].decodeSuccess) {
*nrLDPC_TB_decoding_parameters->processedSegments = *nrLDPC_TB_decoding_parameters->processedSegments + 1;
}
}
}
return 0;
}

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@@ -1,220 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/CODING/nrLDPC_coding/nrLDPC_coding_segment/nrLDPC_coding_segment_encoder.c
* \brief Top-level routines for implementing LDPC encoding of transport channels
*/
#include "PHY/defs_gNB.h"
#include "PHY/CODING/coding_extern.h"
#include "PHY/CODING/coding_defs.h"
#include "PHY/CODING/lte_interleaver_inline.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
#include "PHY/CODING/nrLDPC_extern.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "SCHED_NR/sched_nr.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "common/utils/LOG/log.h"
#include "common/utils/nr/nr_common.h"
#include <syscall.h>
#include <openair2/UTIL/OPT/opt.h>
//#define DEBUG_LDPC_ENCODING
//#define DEBUG_LDPC_ENCODING_FREE 1
extern ldpc_interface_t ldpc_interface_segment;
typedef struct ldpc8blocks_args_s {
nrLDPC_TB_encoding_parameters_t *nrLDPC_TB_encoding_parameters;
encoder_implemparams_t impp;
} ldpc8blocks_args_t;
static void ldpc8blocks_coding_segment(void *p)
{
ldpc8blocks_args_t *args = (ldpc8blocks_args_t *)p;
nrLDPC_TB_encoding_parameters_t *nrLDPC_TB_encoding_parameters = args->nrLDPC_TB_encoding_parameters;
encoder_implemparams_t *impp = &args->impp;
uint8_t mod_order = nrLDPC_TB_encoding_parameters->Qm;
uint16_t nb_rb = nrLDPC_TB_encoding_parameters->nb_rb;
uint32_t A = nrLDPC_TB_encoding_parameters->A;
unsigned int G = nrLDPC_TB_encoding_parameters->G;
LOG_D(PHY,"dlsch coding A %d Kr %d G %d (nb_rb %d, mod_order %d)\n",
A,impp->K,G, nb_rb,(int)mod_order);
// nrLDPC_encoder output is in "d"
// let's make this interface happy!
uint8_t tmp[8][68 * 384]__attribute__((aligned(32)));
uint8_t *d[impp->n_segments];
for (int rr=impp->macro_num*8, i=0; rr < impp->n_segments && rr < (impp->macro_num+1)*8; rr++,i++ )
d[rr] = tmp[i];
uint8_t *c[nrLDPC_TB_encoding_parameters->C];
for (int r = 0; r < nrLDPC_TB_encoding_parameters->C; r++)
c[r]=nrLDPC_TB_encoding_parameters->segments[r].c;
start_meas(&nrLDPC_TB_encoding_parameters->segments[impp->macro_num*8].ts_ldpc_encode);
ldpc_interface_segment.LDPCencoder(c, d, impp);
stop_meas(&nrLDPC_TB_encoding_parameters->segments[impp->macro_num*8].ts_ldpc_encode);
// Compute where to place in output buffer that is concatenation of all segments
uint32_t r_offset=0;
for (int i=0; i < impp->macro_num*8; i++ )
r_offset+=nrLDPC_TB_encoding_parameters->segments[i].E;
for (int rr=impp->macro_num*8; rr < impp->n_segments && rr < (impp->macro_num+1)*8; rr++ ) {
if (impp->F>0) {
// writing into positions d[r][k-2Zc] as in clause 5.3.2 step 2) in 38.212
memset(&d[rr][impp->K - impp->F - 2 * impp->Zc], NR_NULL, impp->F);
}
#ifdef DEBUG_LDPC_ENCODING
LOG_D(PHY,"rvidx in encoding = %d\n", rel15->rvIndex[0]);
#endif
uint32_t E = nrLDPC_TB_encoding_parameters->segments[rr].E;
LOG_D(NR_PHY,
"Rate Matching, Code segment %d/%d (coded bits (G) %u, E %d, Filler bits %d, Filler offset %d mod_order %d, nb_rb "
"%d,nrOfLayer %d)...\n",
rr,
impp->n_segments,
G,
E,
impp->F,
impp->K - impp->F - 2 * impp->Zc,
mod_order,
nb_rb,
nrLDPC_TB_encoding_parameters->nb_layers);
uint32_t Tbslbrm = nrLDPC_TB_encoding_parameters->tbslbrm;
uint8_t e[E];
bzero (e, E);
start_meas(&nrLDPC_TB_encoding_parameters->segments[rr].ts_rate_match);
nr_rate_matching_ldpc(Tbslbrm,
impp->BG,
impp->Zc,
d[rr],
e,
impp->n_segments,
impp->F,
impp->K - impp->F - 2 * impp->Zc,
nrLDPC_TB_encoding_parameters->rv_index,
E);
stop_meas(&nrLDPC_TB_encoding_parameters->segments[rr].ts_rate_match);
if (impp->K - impp->F - 2 * impp->Zc > E) {
LOG_E(PHY,
"dlsch coding A %d Kr %d G %d (nb_rb %d, mod_order %d)\n",
A,
impp->K,
G,
nb_rb,
(int)mod_order);
LOG_E(NR_PHY,
"Rate Matching, Code segment %d/%d (coded bits (G) %u, E %d, Kr %d, Filler bits %d, Filler offset %d mod_order %d, "
"nb_rb %d)...\n",
rr,
impp->n_segments,
G,
E,
impp->K,
impp->F,
impp->K - impp->F - 2 * impp->Zc,
mod_order,
nb_rb);
}
#ifdef DEBUG_LDPC_ENCODING
for (int i =0; i<16; i++)
printf("output ratematching e[%d]= %d r_offset %u\n", i,e[i], r_offset);
#endif
start_meas(&nrLDPC_TB_encoding_parameters->segments[rr].ts_interleave);
nr_interleaving_ldpc(E,
mod_order,
e,
impp->output+r_offset);
stop_meas(&nrLDPC_TB_encoding_parameters->segments[rr].ts_interleave);
#ifdef DEBUG_LDPC_ENCODING
for (int i =0; i<16; i++)
printf("output interleaving f[%d]= %d r_offset %u\n", i,impp->output[i+r_offset], r_offset);
if (r==impp->n_segments-1)
write_output("enc_output.m","enc",impp->output,G,1,4);
#endif
r_offset += E;
}
}
static int nrLDPC_prepare_TB_encoding(nrLDPC_slot_encoding_parameters_t *nrLDPC_slot_encoding_parameters, int dlsch_id)
{
nrLDPC_TB_encoding_parameters_t *nrLDPC_TB_encoding_parameters = &nrLDPC_slot_encoding_parameters->TBs[dlsch_id];
encoder_implemparams_t impp;
impp.n_segments = nrLDPC_TB_encoding_parameters->C;
impp.tinput = nrLDPC_slot_encoding_parameters->tinput;
impp.tprep = nrLDPC_slot_encoding_parameters->tprep;
impp.tparity = nrLDPC_slot_encoding_parameters->tparity;
impp.toutput = nrLDPC_slot_encoding_parameters->toutput;
impp.Kb = nrLDPC_TB_encoding_parameters->Kb;
impp.Zc = nrLDPC_TB_encoding_parameters->Z;
NR_DL_gNB_HARQ_t harq;
impp.harq = &harq;
impp.BG = nrLDPC_TB_encoding_parameters->BG;
impp.output = nrLDPC_TB_encoding_parameters->segments->output;
impp.K = nrLDPC_TB_encoding_parameters->K;
impp.F = nrLDPC_TB_encoding_parameters->F;
impp.Qm = nrLDPC_TB_encoding_parameters->Qm;
impp.Tbslbrm = nrLDPC_TB_encoding_parameters->tbslbrm;
impp.G = nrLDPC_TB_encoding_parameters->G;
for (int r = 0; r < nrLDPC_TB_encoding_parameters->C; r++) {
impp.perCB[r].E_cb = nrLDPC_TB_encoding_parameters->segments[r].E;
}
impp.rv = nrLDPC_TB_encoding_parameters->rv_index;
int nbJobs = 0;
for (int j = 0; j < (impp.n_segments / 8 + ((impp.n_segments & 7) == 0 ? 0 : 1)); j++) {
notifiedFIFO_elt_t *req = newNotifiedFIFO_elt(sizeof(ldpc8blocks_args_t), j, nrLDPC_slot_encoding_parameters->respEncode, ldpc8blocks_coding_segment);
ldpc8blocks_args_t *perJobImpp = (ldpc8blocks_args_t *)NotifiedFifoData(req);
impp.macro_num = j;
perJobImpp->impp = impp;
perJobImpp->nrLDPC_TB_encoding_parameters = nrLDPC_TB_encoding_parameters;
pushTpool(nrLDPC_slot_encoding_parameters->threadPool, req);
nbJobs++;
}
return nbJobs;
}
int nrLDPC_coding_encoder(nrLDPC_slot_encoding_parameters_t *nrLDPC_slot_encoding_parameters)
{
int nbEncode = 0;
for (int dlsch_id = 0; dlsch_id < nrLDPC_slot_encoding_parameters->nb_TBs; dlsch_id++) {
nbEncode += nrLDPC_prepare_TB_encoding(nrLDPC_slot_encoding_parameters, dlsch_id);
}
return nbEncode;
}

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@@ -1,414 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this
* file except in compliance with the License. You may obtain a copy of the
* License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* -------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/CODING/nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma.c
* \brief Top-level routines for decoding LDPC (ULSCH) transport channels
* decoding implemented using a FEC IP core on FPGA through XDMA driver
*/
// [from gNB coding]
#include <syscall.h>
#include "PHY/CODING/coding_defs.h"
#include "PHY/CODING/coding_extern.h"
#include "PHY/CODING/lte_interleaver_inline.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma_offload.h"
#include "PHY/CODING/nrLDPC_extern.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/defs_gNB.h"
#include "SCHED_NR/fapi_nr_l1.h"
#include "SCHED_NR/sched_nr.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "defs.h"
// #define DEBUG_ULSCH_DECODING
// #define gNB_DEBUG_TRACE
#define OAI_UL_LDPC_MAX_NUM_LLR 27000 // 26112 // NR_LDPC_NCOL_BG1*NR_LDPC_ZMAX = 68*384
// #define DEBUG_CRC
#ifdef DEBUG_CRC
#define PRINT_CRC_CHECK(a) a
#else
#define PRINT_CRC_CHECK(a)
#endif
// extern double cpuf;
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_interface.h"
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
// Global var to limit the rework of the dirty legacy code
ldpc_interface_t ldpc_interface_segment;
int num_threads_prepare_max = 0;
/*!
* \typedef args_fpga_decode_prepare_t
* \struct args_fpga_decode_prepare_s
* \brief arguments structure for passing arguments to the nr_ulsch_FPGA_decoding_prepare_blocks function
*/
typedef struct args_fpga_decode_prepare_s {
nrLDPC_TB_decoding_parameters_t *TB_params; /*!< transport blocks parameters */
int8_t *multi_indata; /*!< pointer to the head of the block destination array that is then passed to the FPGA decoding */
int no_iteration_ldpc; /*!< pointer to the number of iteration set by this function */
uint32_t r_first; /*!< index of the first block to be prepared within this function */
uint32_t r_span; /*!< number of blocks to be prepared within this function */
int r_offset; /*!< r index expressed in bits */
int input_CBoffset; /*!< */
int kc; /*!< */
int K_bits_F; /*!< */
} args_fpga_decode_prepare_t;
int32_t nrLDPC_coding_init(void);
int32_t nrLDPC_coding_shutdown(void);
int32_t nrLDPC_coding_decoder(nrLDPC_slot_decoding_parameters_t *slot_params, int frame_rx, int slot_rx);
// int32_t nrLDPC_coding_encoder(void);
int decoder_xdma(nrLDPC_TB_decoding_parameters_t *TB_params,
int frame_rx,
int slot_rx,
tpool_t *ldpc_threadPool,
notifiedFIFO_t *ldpc_respDecode);
void nr_ulsch_FPGA_decoding_prepare_blocks(void *args);
int32_t nrLDPC_coding_init(void)
{
char *encoder_shlibversion = NULL;
paramdef_t LoaderParams[] = {
{"num_threads_prepare", NULL, 0, .iptr = &num_threads_prepare_max, .defintval = 0, TYPE_INT, 0, NULL},
{"encoder_shlibversion", NULL, 0, .strptr = &encoder_shlibversion, .defstrval = "", TYPE_STRING, 0, NULL}
};
config_get(config_get_if(), LoaderParams, sizeofArray(LoaderParams), "nrLDPC_coding_xdma");
AssertFatal(num_threads_prepare_max != 0, "nrLDPC_coding_xdma.num_threads_prepare was not provided");
load_LDPClib(encoder_shlibversion, &ldpc_interface_segment);
return 0;
}
int32_t nrLDPC_coding_shutdown(void)
{
free_LDPClib(&ldpc_interface_segment);
return 0;
}
int32_t nrLDPC_coding_decoder(nrLDPC_slot_decoding_parameters_t *slot_params, int frame_rx, int slot_rx)
{
int nbDecode = 0;
for (int ULSCH_id = 0; ULSCH_id < slot_params->nb_TBs; ULSCH_id++)
nbDecode += decoder_xdma(&slot_params->TBs[ULSCH_id], frame_rx, slot_rx, slot_params->threadPool, slot_params->respDecode);
return nbDecode;
}
/*
int32_t nrLDPC_coding_encoder(void)
{
return 0;
}
*/
int decoder_xdma(nrLDPC_TB_decoding_parameters_t *TB_params,
int frame_rx,
int slot_rx,
tpool_t *ldpc_threadPool,
notifiedFIFO_t *ldpc_respDecode)
{
const uint32_t Kr = TB_params->K;
const uint32_t Kr_bytes = Kr >> 3;
const int kc = TB_params->BG == 2 ? 52 : 68;
int r_offset = 0, offset = 0;
int K_bits_F = Kr - TB_params->F;
// FPGA parameter preprocessing
static int8_t multi_indata[27000 * 25]; // FPGA input data
static int8_t multi_outdata[1100 * 25]; // FPGA output data
int bg_len = TB_params->BG == 1 ? 22 : 10;
// Calc input CB offset
int input_CBoffset = TB_params->Z * kc * 8;
if ((input_CBoffset & 0x7F) == 0)
input_CBoffset = input_CBoffset / 8;
else
input_CBoffset = 16 * ((input_CBoffset / 128) + 1);
DecIFConf dec_conf;
dec_conf.Zc = TB_params->Z;
dec_conf.BG = TB_params->BG;
dec_conf.max_iter = TB_params->max_ldpc_iterations;
dec_conf.numCB = TB_params->C;
// input soft bits length, Zc x 66 - length of filler bits
dec_conf.numChannelLls = (K_bits_F - 2 * TB_params->Z) + (kc * TB_params->Z - Kr);
// filler bits length
dec_conf.numFillerBits = TB_params->F;
dec_conf.max_schedule = 0;
dec_conf.SetIdx = 12;
dec_conf.nRows = (dec_conf.BG == 1) ? 46 : 42;
int out_CBoffset = dec_conf.Zc * bg_len;
if ((out_CBoffset & 0x7F) == 0)
out_CBoffset = out_CBoffset / 8;
else
out_CBoffset = 16 * ((out_CBoffset / 128) + 1);
#ifdef LDPC_DATA
printf("\n------------------------\n");
printf("BG:\t\t%d\n", dec_conf.BG);
printf("TB_params->C: %d\n", TB_params->C);
printf("TB_params->K: %d\n", TB_params->K);
printf("TB_params->Z: %d\n", TB_params->Z);
printf("TB_params->F: %d\n", TB_params->F);
printf("numChannelLls:\t %d = (%d - 2 * %d) + (%d * %d - %d)\n",
dec_conf.numChannelLls,
K_bits_F,
TB_params->Z,
kc,
TB_params->Z,
Kr);
printf("numFillerBits:\t %d\n", TB_params->F);
printf("------------------------\n");
// ===================================
// debug mode
// ===================================
FILE *fptr_llr, *fptr_ldpc;
fptr_llr = fopen("../../../cmake_targets/log/ulsim_ldpc_llr.txt", "w");
fptr_ldpc = fopen("../../../cmake_targets/log/ulsim_ldpc_output.txt", "w");
// ===================================
#endif
int length_dec = lenWithCrc(TB_params->C, TB_params->A);
uint8_t crc_type = crcType(TB_params->C, TB_params->A);
int no_iteration_ldpc = 2;
uint32_t num_threads_prepare = 0;
uint32_t r_remaining = 0;
// start the prepare jobs
for (uint32_t r = 0; r < TB_params->C; r++) {
nrLDPC_segment_decoding_parameters_t *segment_params = &TB_params->segments[r];
if (r_remaining == 0) {
void (*nr_ulsch_FPGA_decoding_prepare_blocks_ptr)(void *) = &nr_ulsch_FPGA_decoding_prepare_blocks;
// TODO: int nr_tti_rx = 0;
union ldpcReqUnion id = {.s = {TB_params->rnti, frame_rx, slot_rx, 0, 0}};
notifiedFIFO_elt_t *req =
newNotifiedFIFO_elt(sizeof(args_fpga_decode_prepare_t), id.p, ldpc_respDecode, nr_ulsch_FPGA_decoding_prepare_blocks_ptr);
args_fpga_decode_prepare_t *args = (args_fpga_decode_prepare_t *)NotifiedFifoData(req);
args->TB_params = TB_params;
args->multi_indata = multi_indata;
args->no_iteration_ldpc = no_iteration_ldpc;
args->r_first = r;
uint32_t r_span_max = ((TB_params->C - r) % (num_threads_prepare_max - num_threads_prepare)) == 0
? (TB_params->C - r) / (num_threads_prepare_max - num_threads_prepare)
: ((TB_params->C - r) / (num_threads_prepare_max - num_threads_prepare)) + 1;
uint32_t r_span = TB_params->C - r < r_span_max ? TB_params->C - r : r_span_max;
args->r_span = r_span;
args->r_offset = r_offset;
args->input_CBoffset = input_CBoffset;
args->kc = kc;
args->K_bits_F = K_bits_F;
r_remaining = r_span;
pushTpool(ldpc_threadPool, req);
LOG_D(PHY, "Added %d block(s) to prepare for decoding, in pipe: %d to %d\n", r_span, r, r + r_span - 1);
num_threads_prepare++;
}
r_offset += segment_params->E;
offset += (Kr_bytes - (TB_params->F >> 3) - ((TB_params->C > 1) ? 3 : 0));
r_remaining -= 1;
}
// reset offset in order to properly fill the output array later
offset = 0;
// wait for the prepare jobs to complete
while (num_threads_prepare > 0) {
notifiedFIFO_elt_t *req = (notifiedFIFO_elt_t *)pullTpool(ldpc_respDecode, ldpc_threadPool);
if (req == NULL)
LOG_E(PHY, "FPGA decoding preparation: pullTpool returned NULL\n");
args_fpga_decode_prepare_t *args = (args_fpga_decode_prepare_t *)NotifiedFifoData(req);
if (args->no_iteration_ldpc > TB_params->max_ldpc_iterations)
no_iteration_ldpc = TB_params->max_ldpc_iterations + 1;
num_threads_prepare -= 1;
}
// launch decode with FPGA
LOG_I(PHY, "Run the LDPC ------[FPGA version]------\n");
//==================================================================
// Xilinx FPGA LDPC decoding function -> nrLDPC_decoder_FPGA_PYM()
//==================================================================
start_meas(&TB_params->segments[0].ts_ldpc_decode);
nrLDPC_decoder_FPGA_PYM((int8_t *)&multi_indata[0], (int8_t *)&multi_outdata[0], dec_conf);
// printf("Xilinx FPGA -> CB = %d\n", harq_process->C);
// nrLDPC_decoder_FPGA_PYM((int8_t *)&temp_multi_indata[0], (int8_t *)&multi_outdata[0], dec_conf);
stop_meas(&TB_params->segments[0].ts_ldpc_decode);
*TB_params->processedSegments = 0;
for (uint32_t r = 0; r < TB_params->C; r++) {
// ------------------------------------------------------------
// --------------------- copy FPGA output ---------------------
// ------------------------------------------------------------
nrLDPC_segment_decoding_parameters_t *segment_params = &TB_params->segments[r];
if (check_crc((uint8_t *)multi_outdata, length_dec, crc_type)) {
#ifdef DEBUG_CRC
LOG_I(PHY, "Segment %d CRC OK\n", r);
#endif
no_iteration_ldpc = 2;
} else {
#ifdef DEBUG_CRC
LOG_I(PHY, "segment %d CRC NOK\n", r);
#endif
no_iteration_ldpc = TB_params->max_ldpc_iterations + 1;
}
for (int i = 0; i < out_CBoffset; i++) {
segment_params->c[i] = (uint8_t)multi_outdata[i + r * out_CBoffset];
}
segment_params->decodeSuccess = (no_iteration_ldpc <= TB_params->max_ldpc_iterations);
if (segment_params->decodeSuccess) {
*TB_params->processedSegments = *TB_params->processedSegments + 1;
}
}
return 0;
}
/*!
* \fn nr_ulsch_FPGA_decoding_prepare_blocks(void *args)
* \brief prepare blocks for LDPC decoding on FPGA
*
* \param args pointer to the arguments of the function in a structure of type args_fpga_decode_prepare_t
*/
void nr_ulsch_FPGA_decoding_prepare_blocks(void *args)
{
// extract the arguments
args_fpga_decode_prepare_t *arguments = (args_fpga_decode_prepare_t *)args;
nrLDPC_TB_decoding_parameters_t *TB_params = arguments->TB_params;
uint8_t Qm = TB_params->Qm;
uint8_t BG = TB_params->BG;
uint8_t rv_index = TB_params->rv_index;
uint8_t max_ldpc_iterations = TB_params->max_ldpc_iterations;
uint32_t tbslbrm = TB_params->tbslbrm;
uint32_t Kr = TB_params->K;
uint32_t Z = TB_params->Z;
uint32_t F = TB_params->F;
uint32_t C = TB_params->C;
nrLDPC_segment_decoding_parameters_t *segment_params = &TB_params->segments[0];
short *ulsch_llr = segment_params->llr;
int8_t *multi_indata = arguments->multi_indata;
int no_iteration_ldpc = arguments->no_iteration_ldpc;
uint32_t r_first = arguments->r_first;
uint32_t r_span = arguments->r_span;
int r_offset = arguments->r_offset;
int input_CBoffset = arguments->input_CBoffset;
int kc = arguments->kc;
int K_bits_F = arguments->K_bits_F;
int16_t z[68 * 384 + 16] __attribute__((aligned(16)));
simde__m128i *pv = (simde__m128i *)&z;
// the function processes r_span blocks starting from block at index r_first in ulsch_llr
for (uint32_t r = r_first; r < (r_first + r_span); r++) {
nrLDPC_segment_decoding_parameters_t *segment_params = &TB_params->segments[r];
// ----------------------- FPGA pre process ------------------------
simde__m128i ones = simde_mm_set1_epi8(255); // Generate a vector with all elements set to 255
simde__m128i *temp_multi_indata = (simde__m128i *)&multi_indata[r * input_CBoffset];
// -----------------------------------------------------------------
// code blocks after bit selection in rate matching for LDPC code (38.212 V15.4.0 section 5.4.2.1)
int16_t harq_e[segment_params->E];
// -------------------------------------------------------------------------------------------
// deinterleaving
// -------------------------------------------------------------------------------------------
start_meas(&segment_params->ts_deinterleave);
nr_deinterleaving_ldpc(segment_params->E, Qm, harq_e, ulsch_llr + r_offset);
stop_meas(&segment_params->ts_deinterleave);
// -------------------------------------------------------------------------------------------
// dematching
// -------------------------------------------------------------------------------------------
start_meas(&segment_params->ts_rate_unmatch);
if (nr_rate_matching_ldpc_rx(tbslbrm,
BG,
Z,
segment_params->d,
harq_e,
C,
rv_index,
*segment_params->d_to_be_cleared,
segment_params->E,
F,
Kr - F - 2 * Z)
== -1) {
stop_meas(&segment_params->ts_rate_unmatch);
LOG_E(PHY, "ulsch_decoding.c: Problem in rate_matching\n");
no_iteration_ldpc = max_ldpc_iterations + 1;
arguments->no_iteration_ldpc = no_iteration_ldpc;
return;
} else {
stop_meas(&segment_params->ts_rate_unmatch);
}
*segment_params->d_to_be_cleared = false;
memset(segment_params->c, 0, Kr >> 3);
// set first 2*Z_c bits to zeros
memset(&z[0], 0, 2 * Z * sizeof(int16_t));
// set Filler bits
memset((&z[0] + K_bits_F), 127, F * sizeof(int16_t));
// Move coded bits before filler bits
memcpy((&z[0] + 2 * Z), segment_params->d, (K_bits_F - 2 * Z) * sizeof(int16_t));
// skip filler bits
memcpy((&z[0] + Kr), segment_params->d + (Kr - 2 * Z), (kc * Z - Kr) * sizeof(int16_t));
// Saturate coded bits before decoding into 8 bits values
for (int i = 0, j = 0; j < ((kc * Z) >> 4); i += 2, j++) {
temp_multi_indata[j] =
simde_mm_xor_si128(simde_mm_packs_epi16(pv[i], pv[i + 1]),
simde_mm_cmpeq_epi32(ones,
ones)); // Perform NOT operation and write the result to temp_multi_indata[j]
}
// the last bytes before reaching "kc * harq_process->Z" should not be written 128 bits at a time to avoid overwritting the
// following block in multi_indata
simde__m128i tmp =
simde_mm_xor_si128(simde_mm_packs_epi16(pv[2 * ((kc * Z) >> 4)], pv[2 * ((kc * Z) >> 4) + 1]),
simde_mm_cmpeq_epi32(ones,
ones)); // Perform NOT operation and write the result to temp_multi_indata[j]
int8_t *tmp_p = (int8_t *)&tmp;
for (int i = 0, j = ((kc * Z) & 0xfffffff0); j < kc * Z; i++, j++) {
multi_indata[r * input_CBoffset + j] = tmp_p[i];
}
r_offset += segment_params->E;
}
arguments->no_iteration_ldpc = no_iteration_ldpc;
}

View File

@@ -1,984 +0,0 @@
/*
* Copyright (c) 2016-present, Xilinx, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license
* the terms of the BSD Licence are reported below:
*
* BSD License
*
* For Xilinx DMA IP software
*
* Copyright (c) 2016-present, Xilinx, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name Xilinx nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define _BSD_SOURCE
#define _XOPEN_SOURCE 500
#include <assert.h>
#include <fcntl.h>
#include <getopt.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <time.h>
#include <byteswap.h>
#include <signal.h>
#include <ctype.h>
#include <termios.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/types.h>
#include "xdma_diag.h"
#include "nrLDPC_coding_xdma_offload.h"
#include "common/utils/assertions.h"
typedef unsigned long long U64;
static struct option const long_opts[] = {{"device", required_argument, NULL, 'd'},
{"address", required_argument, NULL, 'a'},
{"size", required_argument, NULL, 's'},
{"offset", required_argument, NULL, 'o'},
{"count", required_argument, NULL, 'c'},
{"data infile", required_argument, NULL, 'f'},
{"data outfile", required_argument, NULL, 'w'},
{"help", no_argument, NULL, 'h'},
{"verbose", no_argument, NULL, 'v'},
{0, 0, 0, 0}};
#if 0
/* ltoh: little to host */
/* htol: little to host */
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define ltohl(x) (x)
#define ltohs(x) (x)
#define htoll(x) (x)
#define htols(x) (x)
#elif __BYTE_ORDER == __BIG_ENDIAN
#define ltohl(x) __bswap_32(x)
#define ltohs(x) __bswap_16(x)
#define htoll(x) __bswap_32(x)
#define htols(x) __bswap_16(x)
#endif
#define MAP_SIZE (32 * 1024UL)
#define MAP_MASK (MAP_SIZE - 1)
#define DEVICE_NAME_DEFAULT_READ "/dev/xdma0_c2h_1"
#define DEVICE_NAME_DEFAULT_WRITE "/dev/xdma0_h2c_1"
#define SIZE_DEFAULT (32)
#define COUNT_DEFAULT (1)
#define OFFSET_DEC_IN 0x0000
#define OFFSET_DEC_OUT 0x0004
#define OFFSET_ENC_IN 0x0008
#define OFFSET_ENC_OUT 0x000c
#define OFFSET_RESET 0x0020
#define CB_PROCESS_NUMBER 12 // add by JW
#endif
void* map_base;
int fd;
int fd_enc_write, fd_enc_read;
int fd_dec_write, fd_dec_read;
char *allocated_write, *allocated_read;
// dma_from_device.c
#if 0
int test_dma_end_read();
int test_dma_enc_write();
#endif
static int no_write = 0;
// [Start] #include "dma_utils.c" ===================================
/*
* man 2 write:
* On Linux, write() (and similar system calls) will transfer at most
* 0x7ffff000 (2,147,479,552) bytes, returning the number of bytes
* actually transferred. (This is true on both 32-bit and 64-bit
* systems.)
*/
#define RW_MAX_SIZE 0x7ffff000
int verbose = 0;
uint64_t getopt_integer(char* optarg)
{
int rc;
uint64_t value;
rc = sscanf(optarg, "0x%lx", &value);
if (rc <= 0)
rc = sscanf(optarg, "%lu", &value);
// printf("sscanf() = %d, value = 0x%lx\n", rc, value);
return value;
}
ssize_t read_to_buffer(char* fname, int fd, char* buffer, uint64_t size, uint64_t base)
{
ssize_t rc;
uint64_t count = 0;
char* buf = buffer;
off_t offset = base;
while (count < size) {
uint64_t bytes = size - count;
if (bytes > RW_MAX_SIZE)
bytes = RW_MAX_SIZE;
if (offset) {
rc = lseek(fd, offset, SEEK_SET);
if (rc != offset) {
fprintf(stderr, "%s, seek off 0x%lx != 0x%lx.\n", fname, rc, offset);
perror("seek file");
return -EIO;
}
}
/* read data from file into memory buffer */
rc = read(fd, buf, bytes);
if (rc != bytes) {
fprintf(stderr, "%s, R off 0x%lx, 0x%lx != 0x%lx.\n", fname, count, rc, bytes);
perror("read file");
return -EIO;
}
count += bytes;
buf += bytes;
offset += bytes;
}
if (count != size) {
fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", fname, count, size);
return -EIO;
}
return count;
}
ssize_t write_from_buffer(char* fname, int fd, char* buffer, uint64_t size, uint64_t base)
{
ssize_t rc;
uint64_t count = 0;
char* buf = buffer;
off_t offset = base;
while (count < size) {
uint64_t bytes = size - count;
if (bytes > RW_MAX_SIZE)
bytes = RW_MAX_SIZE;
if (offset) {
rc = lseek(fd, offset, SEEK_SET);
if (rc != offset) {
fprintf(stderr, "%s, seek off 0x%lx != 0x%lx.\n", fname, rc, offset);
perror("seek file");
return -EIO;
}
}
/* write data to file from memory buffer */
rc = write(fd, buf, bytes);
if (rc != bytes) {
fprintf(stderr, "%s, W off 0x%lx, 0x%lx != 0x%lx.\n", fname, offset, rc, bytes);
perror("write file");
return -EIO;
}
count += bytes;
buf += bytes;
offset += bytes;
}
if (count != size) {
fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", fname, count, size);
return -EIO;
}
return count;
}
/* Subtract timespec t2 from t1
*
* Both t1 and t2 must already be normalized
* i.e. 0 <= nsec < 1000000000
*/
static int timespec_check(struct timespec* t)
{
if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000))
return -1;
return 0;
}
/*
void timespec_sub(struct timespec* t1, struct timespec* t2)
{
if (timespec_check(t1) < 0) {
fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", (long long)t1->tv_sec, t1->tv_nsec);
return;
}
if (timespec_check(t2) < 0) {
fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", (long long)t2->tv_sec, t2->tv_nsec);
return;
}
t1->tv_sec -= t2->tv_sec;
t1->tv_nsec -= t2->tv_nsec;
if (t1->tv_nsec >= 1000000000) {
t1->tv_sec++;
t1->tv_nsec -= 1000000000;
} else if (t1->tv_nsec < 0) {
t1->tv_sec--;
t1->tv_nsec += 1000000000;
}
}
*/
// [End] #include "dma_utils.c" ===================================
int test_dma_enc_read(char* EncOut, EncIPConf Confparam)
{
// U64 tTotal = MLogPhyTick();
ssize_t rc;
uint64_t i;
void* virt_addr;
uint64_t size;
uint32_t writeval;
uint32_t Z_val;
uint16_t max_schedule, mb, id, bg, z_j, kb, z_a;
uint16_t z_set;
uint32_t ctrl_data;
uint32_t CB_num = CB_PROCESS_NUMBER;
// this values should be given by Shane
max_schedule = 0;
mb = Confparam.mb;
id = CB_num;
bg = Confparam.BGSel - 1;
z_set = Confparam.z_set - 1;
z_j = Confparam.z_j;
if (z_set == 0)
z_a = 2;
else if (z_set == 1)
z_a = 3;
else if (z_set == 2)
z_a = 5;
else if (z_set == 3)
z_a = 7;
else if (z_set == 4)
z_a = 9;
else if (z_set == 5)
z_a = 11;
else if (z_set == 6)
z_a = 13;
else
z_a = 15;
if (bg == 0)
kb = 22;
else if (bg == 1)
kb = 10;
else if (bg == 2)
kb = 9;
else if (bg == 3)
kb = 8;
else
kb = 6;
mb = Confparam.kb_1 + kb;
Z_val = (unsigned int)(z_a << z_j);
ctrl_data = (max_schedule << 30) | ((mb - kb) << 24) | (id << 19) | (bg << 6) | (z_set << 3) | z_j;
// printf("max_schedule:%d (mb - kb):%d id:%d bg:%d z_set:%d z_j:%d\n",max_schedule,(mb - kb),id,bg,z_set,z_j);
uint32_t OutDataNUM = Z_val * mb;
uint32_t Out_dwNumItems_p128;
uint32_t Out_dwNumItems;
if ((OutDataNUM & 0x7F) == 0)
Out_dwNumItems_p128 = OutDataNUM >> 5;
else
Out_dwNumItems_p128 = ((OutDataNUM >> 7) + 1) << 2;
// printf("0x%04x \n",Out_dwNumItems_p128);
Out_dwNumItems = ((Out_dwNumItems_p128 << 2) * CB_num);
// printf("0x%04x \n",Out_dwNumItems);
// MLogPhyTask(PID_DL_FEC_GEN3_R1, tTotal, MLogPhyTick());
size = Out_dwNumItems;
writeval = ctrl_data;
// printf("read : %d byte, ctrl : 0x%08x\n",size,writeval);
/* calculate the virtual address to be accessed */
virt_addr = map_base + OFFSET_ENC_OUT;
/* swap 32-bit endianess if host is not little-endian */
writeval = htoll(writeval);
*((uint32_t*)virt_addr) = writeval;
// MLogPhyTask(PID_DL_FEC_GEN3_R2, tTotal, MLogPhyTick());
if (fd_enc_read < 0) {
fprintf(stderr, "unable to open device %s, %d.\n", DEVICE_NAME_DEFAULT_ENC_READ, fd_enc_read);
perror("open device");
return -EINVAL;
}
/* lseek & read data from AXI MM into buffer using SGDMA */
rc = read_to_buffer(DEVICE_NAME_DEFAULT_ENC_READ, fd_enc_read, EncOut, size, 0);
// rc = read_to_buffer(DEVICE_NAME_DEFAULT_ENC_READ, fd_enc_read, allocated_read, size, 0);
// MLogPhyTask(PID_DL_FEC_GEN3_R3, tTotal, MLogPhyTick());
if (rc < 0)
goto out;
rc = 0;
out:
return rc;
}
int test_dma_enc_write(char* data, EncIPConf Confparam)
{
uint64_t i;
ssize_t rc;
// U64 tTotal = MLogPhyTick();
void* virt_addr;
uint64_t size;
uint32_t writeval;
uint32_t Z_val;
uint16_t max_schedule, mb, id, bg, z_j, kb, z_a;
uint16_t z_set;
uint32_t ctrl_data;
uint32_t CB_num = CB_PROCESS_NUMBER;
// this values should be given by Shane
max_schedule = 0;
mb = Confparam.mb;
id = CB_num;
bg = Confparam.BGSel - 1;
z_set = Confparam.z_set - 1;
z_j = Confparam.z_j;
if (z_set == 0)
z_a = 2;
else if (z_set == 1)
z_a = 3;
else if (z_set == 2)
z_a = 5;
else if (z_set == 3)
z_a = 7;
else if (z_set == 4)
z_a = 9;
else if (z_set == 5)
z_a = 11;
else if (z_set == 6)
z_a = 13;
else
z_a = 15;
if (bg == 0)
kb = 22;
else if (bg == 1)
kb = 10;
else if (bg == 2)
kb = 9;
else if (bg == 3)
kb = 8;
else
kb = 6;
mb = Confparam.kb_1 + kb;
Z_val = (unsigned int)(z_a << z_j);
ctrl_data = (max_schedule << 30) | ((mb - kb) << 24) | (id << 19) | (bg << 6) | (z_set << 3) | z_j;
// printf("max_schedule:%d (mb - kb):%d id:%d bg:%d z_set:%d z_j:%d\n",max_schedule,(mb - kb),id,bg,z_set,z_j);
uint32_t InDataNUM = Z_val * kb;
uint32_t In_dwNumItems_p128;
uint32_t In_dwNumItems;
if ((InDataNUM & 0x7F) == 0)
In_dwNumItems_p128 = InDataNUM >> 5;
else
In_dwNumItems_p128 = ((InDataNUM >> 7) + 1) << 2;
In_dwNumItems = ((In_dwNumItems_p128 << 2) * CB_num);
// MLogPhyTask(PID_DL_FEC_GEN3_W1, tTotal, MLogPhyTick());
size = In_dwNumItems;
writeval = ctrl_data;
/* calculate the virtual address to be accessed */
virt_addr = map_base + OFFSET_ENC_IN;
/* swap 32-bit endianess if host is not little-endian */
writeval = htoll(writeval);
*((uint32_t*)virt_addr) = writeval;
// MLogPhyTask(PID_DL_FEC_GEN3_W2, tTotal, MLogPhyTick());
if (fd_enc_write < 0) {
fprintf(stderr, "unable to open device %s, %d.\n", DEVICE_NAME_DEFAULT_ENC_WRITE, fd_enc_write);
perror("open device");
return -EINVAL;
}
rc = write_from_buffer(DEVICE_NAME_DEFAULT_ENC_WRITE, fd_enc_write, data, size, 0);
// rc = write_from_buffer(DEVICE_NAME_DEFAULT_ENC_WRITE, fd_enc_write, allocated_write, size, 0);
if (rc < 0)
goto out;
// MLogPhyTask(PID_DL_FEC_GEN3_W3, tTotal, MLogPhyTick());
rc = 0;
out:
return rc;
}
// int test_dma_dec_read(unsigned int *DecOut, DecIPConf Confparam)
int test_dma_dec_read(char* DecOut, DecIPConf Confparam)
{
struct timespec read_start_2, read_end_2;
ssize_t rc;
uint64_t i;
void* virt_addr;
uint64_t size;
uint32_t writeval;
uint32_t Z_val;
uint16_t max_schedule, mb, id, bg, z_j, kb, z_a, max_iter, sc_idx;
uint16_t z_set;
uint32_t ctrl_data;
uint32_t CB_num = Confparam.CB_num; // CB_PROCESS_NUMBER_Dec;//
// this values should be given by Shane
max_schedule = 0;
mb = Confparam.mb;
id = CB_num;
bg = Confparam.BGSel - 1;
z_set = Confparam.z_set - 1;
z_j = Confparam.z_j;
// max_iter = 4;
max_iter = 8;
sc_idx = 12;
if (z_set == 0)
z_a = 2;
else if (z_set == 1)
z_a = 3;
else if (z_set == 2)
z_a = 5;
else if (z_set == 3)
z_a = 7;
else if (z_set == 4)
z_a = 9;
else if (z_set == 5)
z_a = 11;
else if (z_set == 6)
z_a = 13;
else
z_a = 15;
if (bg == 0)
kb = 22;
else if (bg == 1)
kb = 10;
else if (bg == 2)
kb = 9;
else if (bg == 3)
kb = 8;
else
kb = 6;
Z_val = (unsigned int)(z_a << z_j);
ctrl_data =
(max_schedule << 30) | ((mb - kb) << 24) | (id << 19) | (max_iter << 13) | (sc_idx << 9) | (bg << 6) | (z_set) << 3 | z_j;
uint32_t OutDataNUM = Z_val * kb;
uint32_t Out_dwNumItems_p128;
uint32_t Out_dwNumItems;
if (CB_num & 0x01) // odd cb number
{
if ((OutDataNUM & 0xFF) == 0)
Out_dwNumItems_p128 = OutDataNUM;
else
Out_dwNumItems_p128 = 256 * ((OutDataNUM / 256) + 1);
Out_dwNumItems = (Out_dwNumItems_p128 * CB_num) >> 3;
// printf("Z_val%d CB_num%d OutDataNUM%d Out_dwNumItems_p128%d Out_dwNumItems%d\n" , Z_val, CB_num, OutDataNUM,
// Out_dwNumItems_p128, Out_dwNumItems);
} else {
if ((OutDataNUM & 0x7F) == 0)
Out_dwNumItems_p128 = OutDataNUM;
else
Out_dwNumItems_p128 = 128 * ((OutDataNUM / 128) + 1);
Out_dwNumItems = (Out_dwNumItems_p128 * CB_num) >> 3;
// printf("Z_val%d CB_num%d OutDataNUM%d Out_dwNumItems_p128%d Out_dwNumItems%d\n" , Z_val, CB_num, OutDataNUM,
// Out_dwNumItems_p128, Out_dwNumItems);
if ((Out_dwNumItems & 0x1f) != 0)
Out_dwNumItems = ((Out_dwNumItems + 31) >> 5) << 5;
// printf("Z_val%d kb%d OutDataNUM%d Out_dwNumItems_p128%d Out_dwNumItems%d CB_num=%d\n" , Z_val, kb, OutDataNUM,
// Out_dwNumItems_p128, Out_dwNumItems, CB_num);
}
size = Out_dwNumItems;
writeval = ctrl_data;
/* calculate the virtual address to be accessed */
virt_addr = map_base + OFFSET_DEC_OUT;
/* swap 32-bit endianess if host is not little-endian */
writeval = htoll(writeval);
*((uint32_t*)virt_addr) = writeval;
if (fd_dec_read < 0) {
fprintf(stderr, "unable to open device %s, %d.\n", DEVICE_NAME_DEFAULT_DEC_READ, fd_dec_read);
perror("open device");
return -EINVAL;
}
// clock_gettime(CLOCK_MONOTONIC, &read_start_2);
/* lseek & read data from AXI MM into buffer using SGDMA */
rc = read_to_buffer(DEVICE_NAME_DEFAULT_DEC_READ, fd_dec_read, DecOut, size, 0);
if (rc < 0)
goto out;
rc = 0;
// clock_gettime(CLOCK_MONOTONIC, &read_end_2);
// timespec_sub(&read_end_2, &read_start_2);
// printf("[2]read_to_buffer() time %.2f µsec\n", (float)(read_end_2.tv_nsec) / 1000);
out:
return rc;
}
// int test_dma_dec_write(unsigned int *data, DecIPConf Confparam)
int test_dma_dec_write(char* data, DecIPConf Confparam)
{
uint64_t i;
ssize_t rc;
void* virt_addr;
uint64_t size;
uint32_t writeval;
uint32_t Z_val;
uint16_t max_schedule, mb, id, bg, z_j, kb, z_a, max_iter, sc_idx;
uint16_t z_set;
uint32_t ctrl_data;
uint32_t CB_num = Confparam.CB_num; // CB_PROCESS_NUMBER_Dec;//
// this values should be given by Shane
max_schedule = 0;
mb = Confparam.mb;
id = CB_num;
bg = Confparam.BGSel - 1;
z_set = Confparam.z_set - 1;
z_j = Confparam.z_j;
// max_iter = 4;
max_iter = 8;
sc_idx = 12;
if (z_set == 0)
z_a = 2;
else if (z_set == 1)
z_a = 3;
else if (z_set == 2)
z_a = 5;
else if (z_set == 3)
z_a = 7;
else if (z_set == 4)
z_a = 9;
else if (z_set == 5)
z_a = 11;
else if (z_set == 6)
z_a = 13;
else
z_a = 15;
if (bg == 0)
kb = 22;
else if (bg == 1)
kb = 10;
else if (bg == 2)
kb = 9;
else if (bg == 3)
kb = 8;
else
kb = 6;
Z_val = (unsigned int)(z_a << z_j);
ctrl_data =
(max_schedule << 30) | ((mb - kb) << 24) | (id << 19) | (max_iter << 13) | (sc_idx << 9) | (bg << 6) | (z_set) << 3 | z_j;
uint32_t InDataNUM = Z_val * mb;
uint32_t In_dwNumItems_p128;
uint32_t In_dwNumItems;
InDataNUM = Z_val * mb * 8;
if ((InDataNUM & 0x7F) == 0)
In_dwNumItems_p128 = InDataNUM;
else
In_dwNumItems_p128 = 128 * ((InDataNUM / 128) + 1);
In_dwNumItems = (In_dwNumItems_p128 * CB_num) >> 3;
if ((In_dwNumItems & 0x1f) != 0)
In_dwNumItems = ((In_dwNumItems + 31) >> 5) << 5;
// printf("Z_val[%d] CB_num[%d] mb[%d] InDataNUM[%d] In_dwNumItems_p128[%d] In_dwNumItems[%d]\n" , Z_val, CB_num, mb, InDataNUM,
// In_dwNumItems_p128, In_dwNumItems);
size = In_dwNumItems;
writeval = ctrl_data;
/* calculate the virtual address to be accessed */
virt_addr = map_base + OFFSET_DEC_IN;
/* swap 32-bit endianess if host is not little-endian */
writeval = htoll(writeval);
*((uint32_t*)virt_addr) = writeval;
if (fd_dec_write < 0) {
fprintf(stderr, "unable to open device %s, %d.\n", DEVICE_NAME_DEFAULT_DEC_WRITE, fd_dec_write);
perror("open device");
return -EINVAL;
}
rc = write_from_buffer(DEVICE_NAME_DEFAULT_DEC_WRITE, fd_dec_write, data, size, 0);
if (rc < 0)
goto out;
rc = 0;
out:
return rc;
}
void test_dma_init()
{
/* access width */
int access_width = 'w';
char* device2 = "/dev/xdma0_user"; //
uint32_t size1 = 24 * 1024;
uint32_t size2 = 24 * 1024 * 3;
// printf("\n###################################################\n");
AssertFatal((fd = open(device2, O_RDWR | O_SYNC)) != -1, "CHARACTER DEVICE %s OPEN FAILURE\n", device2);
// printf("# CHARACTER DEVICE %s OPENED. #\n", device2);
fflush(stdout);
/* map one page */
map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
AssertFatal(map_base != (void*)-1, "MEMORY MAP AT ADDRESS %p FAILED\n", map_base);
// printf("# MEMORY MAPPED AT ADDRESS %p. #\n", map_base);
// printf("###################################################\n\n");
void* virt_addr;
virt_addr = map_base + OFFSET_RESET;
*((uint32_t*)virt_addr) = 1;
fd_enc_write = open(DEVICE_NAME_DEFAULT_ENC_WRITE, O_RDWR);
fd_enc_read = open(DEVICE_NAME_DEFAULT_ENC_READ, O_RDWR);
fd_dec_write = open(DEVICE_NAME_DEFAULT_DEC_WRITE, O_RDWR);
fd_dec_read = open(DEVICE_NAME_DEFAULT_DEC_READ, O_RDWR);
fflush(stdout);
allocated_write = NULL;
posix_memalign((void**)&allocated_write, 4096 /*alignment */, size1 + 4096);
allocated_read = NULL;
posix_memalign((void**)&allocated_read, 4096 /*alignment */, size2 + 4096);
}
void dma_reset()
{
char* device2 = "/dev/xdma0_user"; //
void* virt_addr;
virt_addr = map_base + PCIE_OFF;
*((uint32_t*)virt_addr) = 1;
AssertFatal(munmap(map_base, MAP_SIZE) != -1, "munmap failure");
close(fd_enc_write);
close(fd_enc_read);
close(fd_dec_write);
close(fd_dec_read);
close(fd);
// printf("\n###################################################\n");
AssertFatal((fd = open(device2, O_RDWR | O_SYNC)) != -1, "CHARACTER DEVICE %s OPEN FAILURE\n", device2);
// printf("# CHARACTER DEVICE %s OPENED. #\n", device2);
fflush(stdout);
/* map one page */
map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
AssertFatal(map_base != (void*)-1, "MEMORY MAP AT ADDRESS %p FAILED\n", map_base);
// printf("# MEMORY MAPPED AT ADDRESS %p. #\n", map_base);
// printf("###################################################\n\n");
// void *virt_addr;
virt_addr = map_base + PCIE_OFF;
*((uint32_t*)virt_addr) = 1;
// void *virt_addr;
virt_addr = map_base + OFFSET_RESET;
*((uint32_t*)virt_addr) = 1;
fd_enc_write = open(DEVICE_NAME_DEFAULT_ENC_WRITE, O_RDWR);
fd_enc_read = open(DEVICE_NAME_DEFAULT_ENC_READ, O_RDWR);
fd_dec_write = open(DEVICE_NAME_DEFAULT_DEC_WRITE, O_RDWR);
fd_dec_read = open(DEVICE_NAME_DEFAULT_DEC_READ, O_RDWR);
fflush(stdout);
}
void test_dma_shutdown()
{
free(allocated_write);
free(allocated_read);
}
#if 1
// reg_rx.c
int nrLDPC_decoder_FPGA_PYM(int8_t* buf_in, int8_t* buf_out, DecIFConf dec_conf)
{
struct timespec ts_start, ts_end; // evaluate core xdma run time
struct timespec ts_start0, ts_end0; // ealuate time from input setting to output setting include xdma
struct timespec read_start, read_end;
struct timespec write_start, write_end;
int Zc;
int nRows;
int baseGraph;
int CB_num;
DecIPConf Confparam;
int z_a, z_tmp, ii, jj, i;
int z_j = 0;
int numChannelLlrs; // input soft bits length, Zc x 66 - length of filler bits
int numFillerBits; // filler bits length
char in_softbits[26112 * 52 + 1]; // Random by default value, 52 is max CBs in UL 272RBs and 2 layers with 64QAM
char out_MessageBytes[1056 * 52 + 1]; // 52 = max number of code block
int iterationAtTermination; // output results
int parityPassedAtTermination; // output results
// char buffer_in[26112 * 52 + 1];
char buffer_out[1056 * 52 + 1];
int numMsgBits, numMsgBytes, input_CBoffset, output_CBoffset;
uint8_t i_LS;
static int init_flag = 0;
if (init_flag == 0) {
/*Init*/
test_dma_init();
init_flag = 1;
} else {
dma_reset();
}
clock_gettime(CLOCK_MONOTONIC, &ts_start0); // time start0
// LDPC input parameter
Zc = dec_conf.Zc; // shifting size
nRows = dec_conf.nRows; // number of Rows
baseGraph = dec_conf.BG; // base graph
CB_num = dec_conf.numCB; // 31 number of code block
numChannelLlrs = dec_conf.numChannelLls; // input soft bits length, Zc x 66 - length of filler bits
numFillerBits = dec_conf.numFillerBits; // filler bits length
// calc xdma LDPC parameter
// calc i_LS
if ((Zc % 15) == 0)
i_LS = 7;
else if ((Zc % 13) == 0)
i_LS = 6;
else if ((Zc % 11) == 0)
i_LS = 5;
else if ((Zc % 9) == 0)
i_LS = 4;
else if ((Zc % 7) == 0)
i_LS = 3;
else if ((Zc % 5) == 0)
i_LS = 2;
else if ((Zc % 3) == 0)
i_LS = 1;
else
i_LS = 0;
// calc z_a
if (i_LS == 0)
z_a = 2;
else
z_a = i_LS * 2 + 1;
// calc z_j
z_tmp = Zc / z_a;
while (z_tmp % 2 == 0) {
z_j = z_j + 1;
z_tmp = z_tmp / 2;
}
// calc CB_num and mb
Confparam.CB_num = CB_num;
if (baseGraph == 1)
Confparam.mb = 22 + nRows;
else
Confparam.mb = 10 + nRows;
// set BGSel, z_set, z_j
Confparam.BGSel = baseGraph;
Confparam.z_set = i_LS + 1;
Confparam.z_j = z_j;
// calc output numMsgBits
if (baseGraph == 1)
numMsgBits = Zc * 22 - numFillerBits;
else
numMsgBits = Zc * 10 - numFillerBits;
// Calc input CB offset
input_CBoffset = Zc * Confparam.mb * 8;
if ((input_CBoffset & 0x7F) == 0)
input_CBoffset = input_CBoffset / 8;
else
input_CBoffset = 16 * ((input_CBoffset / 128) + 1);
// Calc output CB offset
output_CBoffset = Zc * (Confparam.mb - nRows);
if ((output_CBoffset & 0x7F) == 0)
output_CBoffset = output_CBoffset / 8;
else
output_CBoffset = 16 * ((output_CBoffset / 128) + 1);
// memset(buf_in, 0, 26112 * 52 + 1);
// memset(buf_out, 0, 27500); // memset(buffer_out, 0, 1056 * 52 + 1);
#if 1 // Input Setting FPGA
// set input buffer_in from the llr output (in_softbits)
// Arrange data format
// for (jj = 0; jj < CB_num; jj++) {
// for (ii = 0; ii < (numChannelLlrs + numFillerBits + Zc * 2); ii++) {
// if (buf_in[ii + input_CBoffset * jj] == -128) {
// buf_in[ii + input_CBoffset * jj] = -127;
// }
// if (ii < Zc * 2)
// buf_in[ii + input_CBoffset * jj] = 0x00;
// else if (ii < numMsgBits)
// buf_in[ii + input_CBoffset * jj] = ((buf_in[ii - Zc * 2 + numChannelLlrs * jj]) ^ (0xFF)) + 1;
// else if (ii < (numMsgBits + numFillerBits))
// buf_in[ii + input_CBoffset * jj] = 0x80;
// else
// buf_in[ii + input_CBoffset * jj] = ((buf_in[ii - Zc * 2 - numFillerBits + numChannelLlrs * jj]) ^ (0xFF)) + 1;
// }
// printf("\nInput_LLR[%d] = ", jj);
// for (i = 0; i < 20; i++) {
// printf("%d,", buf_in[i + input_CBoffset * jj + 2 * Zc]);
// }
// }
// printf("input setting done\n");
#endif // Input Setting FPGA
// LDPC accelerator start
// printf("[%s] Start DMA write\n", __func__);
// clock_gettime(CLOCK_MONOTONIC, &ts_start); // time start
// ===================================================
// printf("[%s] DMA write 0\n", __func__);
// write into accelerator
// clock_gettime(CLOCK_MONOTONIC, &write_start);
if (test_dma_dec_write(buf_in, Confparam) != 0) {
exit(1);
printf("write exit!!\n");
}
// clock_gettime(CLOCK_MONOTONIC, &write_end);
// timespec_sub(&write_end, &write_start);
// printf("Write time %.2f µsec\n", (float)(write_end.tv_nsec) / 1000);
// ===================================================
// printf("[%s] DMA read 0\n", __func__);
// read output of accelerator
// clock_gettime(CLOCK_MONOTONIC, &read_start);
if (test_dma_dec_read(buf_out, Confparam) != 0) {
exit(1);
printf("read exit!!\n");
}
// clock_gettime(CLOCK_MONOTONIC, &read_end);
// timespec_sub(&read_end, &read_start);
// printf("[1]Read time %.2f µsec\n", (float)(read_end.tv_nsec) / 1000);
// // ===================================================
// clock_gettime(CLOCK_MONOTONIC, &ts_end); // time end
// printf("[%s] End DMA read\n", __func__);
// LDPC accelerator end
// timespec_sub(&ts_end, &ts_start);
// printf("[%s] finish DMA, CB_num[%d], total time %ld nsec\n", __func__, CB_num, ts_end.tv_nsec);
#if 1 // Output Setting FPGA
// set output out_MessageBytes from the xdma output (buffer_out) , iterationAtTermination , parityPassedAtTermination
for (jj = 0; jj < CB_num; jj++) {
if ((numMsgBits & 0x7) == 0)
numMsgBytes = numMsgBits / 8;
else {
numMsgBytes = (numMsgBits / 8) + 1;
}
iterationAtTermination = 1; // output
parityPassedAtTermination = 1; // output
// memcpy((int8_t*)&buf_out[output_CBoffset * jj], (int8_t*)&buffer_out[output_CBoffset * jj], numMsgBytes);
// -----------------------------------
// Compare output information:
// -----------------------------------
// printf("buffer_out[%d] = ", jj);
// for (i = 0; i < 10; i++) {
// printf("%d, ", buffer_out[i + output_CBoffset * jj]);
// }
// printf("\n");
// printf("buf_out[%d] = ", jj);
// for (i = 0; i < 10; i++) {
// printf("%d, ", buf_out[i + output_CBoffset * jj]);
// }
// printf("\n");
}
// printf("[%s] Output setting done\n", __func__);
#endif // Output Setting FPGA
// clock_gettime(CLOCK_MONOTONIC, &ts_end0); // time end0
// timespec_sub(&ts_end0, &ts_start0);
// printf("[%s] finish LDPC, CB_num[%d], total time %ld nsec\n", __func__, CB_num, ts_end0.tv_nsec);
// printf("Accelerator card is completed!\n");
return 0;
}
#endif

View File

@@ -1,62 +0,0 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this
* file except in compliance with the License. You may obtain a copy of the
* License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* -------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/CODING/nrLDPC_coding/nrLDPC_coding_xdma/nrLDPC_coding_xdma_offload.h
* \briefFPGA accelerator integrated into OAI (for one and multi code block)
* \author Sendren Xu, SY Yeh(fdragon), Hongming, Terng-Yin Hsu
* \date 2022-05-31
* \version 5.0
* \email: summery19961210@gmail.com
*/
#include <stdint.h>
#ifndef __NRLDPC_CODING_XDMA_OFFLOAD__H_
#define __NRLDPC_CODING_XDMA_OFFLOAD__H_
/**
\brief LDPC input parameter
\param Zc shifting size
\param Rows
\param baseGraph base graph
\param CB_num number of code block
\param numChannelLlrs input soft bits length, Zc x 66 - length of filler bits
\param numFillerBits filler bits length
*/
typedef struct {
unsigned char max_schedule;
unsigned char SetIdx;
int Zc;
unsigned char numCB;
unsigned char BG;
unsigned char max_iter;
int nRows;
int numChannelLls;
int numFillerBits;
} DecIFConf;
int nrLDPC_decoder_FPGA_8038(int8_t *buf_in, int8_t *buf_out, DecIFConf dec_conf);
int nrLDPC_decoder_FPGA_PYM(int8_t *buf_in, int8_t *buf_out, DecIFConf dec_conf);
// int nrLDPC_decoder_FPGA_PYM();
#endif // __NRLDPC_CODING_XDMA_OFFLOAD__H_

View File

@@ -1,138 +0,0 @@
/*
* Copyright (c) 2016-present, Xilinx, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license
* the terms of the BSD Licence are reported below:
*
* BSD License
*
* For Xilinx DMA IP software
*
* Copyright (c) 2016-present, Xilinx, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name Xilinx nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef MODULES_TXCTRL_INC_XDMA_DIAG_H_
#define MODULES_TXCTRL_INC_XDMA_DIAG_H_
#ifdef __cplusplus
extern "C" {
#endif
// #define _BSD_SOURCE
// #define _XOPEN_SOURCE 500
// #include "../../LDPC/LDPC_api.h"
// #include "dma_utils.c"
/*static struct option const long_opts[] = {
{"device", required_argument, NULL, 'd'},
{"address", required_argument, NULL, 'a'},
{"size", required_argument, NULL, 's'},
{"offset", required_argument, NULL, 'o'},
{"count", required_argument, NULL, 'c'},
{"data infile", required_argument, NULL, 'f'},
{"data outfile", required_argument, NULL, 'w'},
{"help", no_argument, NULL, 'h'},
{"verbose", no_argument, NULL, 'v'},
{0, 0, 0, 0}
};*/
typedef struct {
unsigned char max_schedule; // max_schedule = 0;
unsigned char mb; // mb = 32;
unsigned char CB_num; // id = CB_num;
unsigned char BGSel; // bg = 1;
unsigned char z_set; // z_set = 0;
unsigned char z_j; // z_j = 6;
unsigned char max_iter; // max_iter = 8;
unsigned char SetIdx; // sc_idx = 12;
} DecIPConf;
typedef struct {
int SetIdx;
int NumCBSegm;
int PayloadLen;
int Z;
int z_set;
int z_j;
int Kbmax;
int BGSel;
unsigned mb;
unsigned char CB_num;
unsigned char kb_1;
} EncIPConf;
/* ltoh: little to host */
/* htol: little to host */
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define ltohl(x) (x)
#define ltohs(x) (x)
#define htoll(x) (x)
#define htols(x) (x)
#elif __BYTE_ORDER == __BIG_ENDIAN
#define ltohl(x) __bswap_32(x)
#define ltohs(x) __bswap_16(x)
#define htoll(x) __bswap_32(x)
#define htols(x) __bswap_16(x)
#endif
#define MAP_SIZE (32 * 1024UL)
#define MAP_MASK (MAP_SIZE - 1)
#define DEVICE_NAME_DEFAULT_ENC_READ "/dev/xdma0_c2h_1"
#define DEVICE_NAME_DEFAULT_ENC_WRITE "/dev/xdma0_h2c_1"
#define DEVICE_NAME_DEFAULT_DEC_READ "/dev/xdma0_c2h_0"
#define DEVICE_NAME_DEFAULT_DEC_WRITE "/dev/xdma0_h2c_0"
#define SIZE_DEFAULT (32)
#define COUNT_DEFAULT (1)
#define OFFSET_DEC_IN 0x0000
#define OFFSET_DEC_OUT 0x0004
#define OFFSET_ENC_IN 0x0008
#define OFFSET_ENC_OUT 0x000c
#define OFFSET_RESET 0x0020
#define PCIE_OFF 0x0030
#define CB_PROCESS_NUMBER 24 // add by JW
#define CB_PROCESS_NUMBER_Dec 24
// dma_from_device.c
int test_dma_enc_read(char *EncOut, EncIPConf Confparam);
int test_dma_enc_write(char *data, EncIPConf Confparam);
int test_dma_dec_read(char *DecOut, DecIPConf Confparam);
int test_dma_dec_write(char *data, DecIPConf Confparam);
void test_dma_init();
void test_dma_shutdown();
void dma_reset();
#ifdef __cplusplus
}
#endif
#endif

View File

@@ -1,394 +0,0 @@
####################################################################################
###### nr_ulsim unit test ######
####################################################################################
set(default_ldpc "")
set(slot_segment "-O" "${CMAKE_CURRENT_SOURCE_DIR}/slot_segment.conf")
set(t2_offload_nr_ulsim "-o" "-O" "${CMAKE_CURRENT_SOURCE_DIR}/t2_offload.conf")
set(slot_t2 "-O" "${CMAKE_CURRENT_SOURCE_DIR}/slot_t2.conf")
set(xdma "-O" "${CMAKE_CURRENT_SOURCE_DIR}/xdma.conf")
set(NR_ULSIM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_ULSIM_OPTION_TO_TEST_LIST
t2_offload_nr_ulsim
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_ULSIM_OPTION_TO_TEST_LIST
xdma
)
endif()
set(test_nr_ulsim_misc_test1 "-n100" "-m9" "-r106" "-s5")
set(test_nr_ulsim_misc_test2 "-n100" "-m16" "-s10")
set(test_nr_ulsim_misc_test3 "-n100" "-m28" "-s20")
set(test_nr_ulsim_misc_test4 "-n100" "-m27" "-s25" "-q1")
set(test_nr_ulsim_misc_test5 "-n100" "-m9" "-R217" "-r217" "-s5")
set(test_nr_ulsim_misc_test6 "-n100" "-m9" "-R273" "-r273" "-s5")
set(test_nr_ulsim_misc_test7 "-n100" "-s5" "-U0,1,1,1")
set(test_nr_ulsim_misc_test8 "-n100" "-s5" "-T1,2" "-U0,2,1,1")
set(test_nr_ulsim_misc_test9 "-n100" "-s5" "-T2,2" "-U1,2,1,1")
set(test_nr_ulsim_misc_test10 "-n100" "-s5" "-a4" "-b8" "-T1,2" "-U1,3,1,1")
set(test_nr_ulsim_misc_test11 "-n100" "-u0" "-m0" "-R25" "-r25" "-i1,0")
set(test_nr_ulsim_misc_test12 "-n100" "-m0" "-S" "-0.6" "-i1,0")
set(test_nr_ulsim_misc_test13 "-n100" "-m28" "-R106" "-r106" "-t90" "-s24" "-S24" "-d8")
set(test_nr_ulsim_sc_test1 "-n100" "-s5" "-Z")
set(test_nr_ulsim_sc_test2 "-n100" "-s5" "-Z" "-r75")
set(test_nr_ulsim_sc_test3 "-n50" "-s5" "-Z" "-r216" "-R217")
set(test_nr_ulsim_sc_test4 "-n50" "-s5" "-Z" "-r270" "-R273")
set(test_nr_ulsim_sc_test5 "-n100" "-s5" "-Z" "-U0,2,1,2")
set(test_nr_ulsim_mimo_test1 "-n100" "-m19" "-s10" "-S15" "-z2")
set(test_nr_ulsim_mimo_test2 "-n100" "-m9" "-r106" "-s8" "-W2" "-y2" "-z2")
set(test_nr_ulsim_mimo_test3 "-n100" "-m10" "-r106" "-s12" "-W2" "-y2" "-z2")
set(test_nr_ulsim_mimo_test4 "-n100" "-m19" "-r106" "-s22" "-W2" "-y2" "-z2")
set(test_nr_ulsim_mimo_test5 "-n100" "-m9" "-r106" "-s10" "-W4" "-y4" "-z4")
set(test_nr_ulsim_3gpp_test1 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U0,1,1,2" "-z2" "-s12.4" "-S12.4")
set(test_nr_ulsim_3gpp_test2 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U0,1,1,2" "-z4" "-s8.5" "-S8.5")
set(test_nr_ulsim_3gpp_test3 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U0,1,1,2" "-z8" "-s5.4" "-S5.4")
set(test_nr_ulsim_3gpp_test4 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R25" "-r25" "-U1,1,1,2" "-z2" "-s12.5" "-S12.5")
set(test_nr_ulsim_3gpp_test5 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R25" "-r25" "-U1,1,1,2" "-z4" "-s8.9" "-S8.9")
set(test_nr_ulsim_3gpp_test6 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R25" "-r25" "-U1,1,1,2" "-z8" "-s5.7" "-S5.7")
set(test_nr_ulsim_3gpp_test7 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R52" "-r52" "-U1,1,1,2" "-z2" "-s12.6" "-S12.6")
set(test_nr_ulsim_3gpp_test8 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R52" "-r52" "-U1,1,1,2" "-z4" "-s8.9" "-S8.9")
set(test_nr_ulsim_3gpp_test9 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R52" "-r52" "-U1,1,1,2" "-z8" "-s5.8" "-S5.8")
set(test_nr_ulsim_3gpp_test10 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z2" "-s12.3" "-S12.3")
set(test_nr_ulsim_3gpp_test11 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z4" "-s8.8" "-S8.8")
set(test_nr_ulsim_3gpp_test12 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u0" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z8" "-s5.7" "-S5.7")
set(test_nr_ulsim_3gpp_test13 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R24" "-r24" "-U1,1,1,2" "-z2" "-s12.5" "-S12.5")
set(test_nr_ulsim_3gpp_test14 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R24" "-r24" "-U1,1,1,2" "-z4" "-s8.6" "-S8.6")
set(test_nr_ulsim_3gpp_test15 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R24" "-r24" "-U1,1,1,2" "-z8" "-s5.6" "-S5.6")
set(test_nr_ulsim_3gpp_test16 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R51" "-r51" "-U1,1,1,2" "-z2" "-s12.5" "-S12.5")
set(test_nr_ulsim_3gpp_test17 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R51" "-r51" "-U1,1,1,2" "-z4" "-s8.6" "-S8.6")
set(test_nr_ulsim_3gpp_test18 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R51" "-r51" "-U1,1,1,2" "-z8" "-s5.6" "-S5.6")
set(test_nr_ulsim_3gpp_test19 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z2" "-s12.5" "-S12.5")
set(test_nr_ulsim_3gpp_test20 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z4" "-s8.7" "-S8.7")
set(test_nr_ulsim_3gpp_test21 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R106" "-r106" "-U1,1,1,2" "-z8" "-s5.5" "-S5.5")
set(test_nr_ulsim_3gpp_test22 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R273" "-r273" "-U1,1,1,2" "-z2" "-s13.1" "-S13.1")
set(test_nr_ulsim_3gpp_test23 "-n100" "-b14" "-I7" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R273" "-r273" "-U1,1,1,2" "-z4" "-s9.2" "-S9.2")
set(test_nr_ulsim_3gpp_test24 "-n100" "-b14" "-I8" "-i0,1" "-gA,l,10" "-t70" "-u1" "-m20" "-R273" "-r273" "-U1,1,1,2" "-z8" "-s5.9" "-S5.9")
set(test_nr_ulsim_3gpp_test25 "-n100" "-b14" "-I15" "-i0,1" "-gB,l" "-t70" "-u1" "-m2" "-R106" "-r106" "-U1,1,1,2" "-W2" "-y2" "-z2" "-s1.7" "-S1.7")
set(test_nr_ulsim_3gpp_test26 "-n100" "-b14" "-I15" "-i0,1" "-gB,l" "-t70" "-u1" "-m2" "-R106" "-r106" "-U1,1,1,2" "-W2" "-y2" "-z4" "-s-2.1" "-S-2.1")
set(test_nr_ulsim_3gpp_test27 "-n100" "-b14" "-I15" "-i0,1" "-gC,l" "-t70" "-u1" "-m16" "-R106" "-r106" "-U1,1,1,2" "-W2" "-y2" "-z2" "-s18.7" "-S18.7")
set(test_nr_ulsim_3gpp_test28 "-n100" "-b14" "-I15" "-i0,1" "-gC,l" "-t70" "-u1" "-m16" "-R106" "-r106" "-U1,1,1,2" "-W2" "-y2" "-z4" "-s11.2" "-S11.2")
set(NR_ULSIM_TEST_CASE_OPTION_LIST
test_nr_ulsim_misc_test1
test_nr_ulsim_misc_test2
test_nr_ulsim_misc_test3
test_nr_ulsim_misc_test4
test_nr_ulsim_misc_test5
test_nr_ulsim_misc_test6
test_nr_ulsim_misc_test7
test_nr_ulsim_misc_test8
test_nr_ulsim_misc_test9
test_nr_ulsim_misc_test10
test_nr_ulsim_misc_test11
test_nr_ulsim_misc_test12
test_nr_ulsim_misc_test13
test_nr_ulsim_sc_test1
test_nr_ulsim_sc_test2
test_nr_ulsim_sc_test3
test_nr_ulsim_sc_test4
test_nr_ulsim_sc_test5
test_nr_ulsim_mimo_test1
test_nr_ulsim_mimo_test2
test_nr_ulsim_mimo_test3
test_nr_ulsim_mimo_test4
test_nr_ulsim_mimo_test5
test_nr_ulsim_3gpp_test1
test_nr_ulsim_3gpp_test2
test_nr_ulsim_3gpp_test3
test_nr_ulsim_3gpp_test4
test_nr_ulsim_3gpp_test5
test_nr_ulsim_3gpp_test6
test_nr_ulsim_3gpp_test7
test_nr_ulsim_3gpp_test8
test_nr_ulsim_3gpp_test9
test_nr_ulsim_3gpp_test10
test_nr_ulsim_3gpp_test11
test_nr_ulsim_3gpp_test12
test_nr_ulsim_3gpp_test13
test_nr_ulsim_3gpp_test14
test_nr_ulsim_3gpp_test15
test_nr_ulsim_3gpp_test16
test_nr_ulsim_3gpp_test17
test_nr_ulsim_3gpp_test18
test_nr_ulsim_3gpp_test19
test_nr_ulsim_3gpp_test20
test_nr_ulsim_3gpp_test21
test_nr_ulsim_3gpp_test22
test_nr_ulsim_3gpp_test23
test_nr_ulsim_3gpp_test24
test_nr_ulsim_3gpp_test25
test_nr_ulsim_3gpp_test26
test_nr_ulsim_3gpp_test27
test_nr_ulsim_3gpp_test28
)
foreach(NR_ULSIM_OPTION_TO_TEST IN LISTS NR_ULSIM_OPTION_TO_TEST_LIST)
foreach(NR_ULSIM_TEST_CASE IN LISTS NR_ULSIM_TEST_CASE_OPTION_LIST)
add_test(
NAME ${NR_ULSIM_TEST_CASE}_${NR_ULSIM_OPTION_TO_TEST}
COMMAND nr_ulsim -P -C1 ${${NR_ULSIM_TEST_CASE}} ${${NR_ULSIM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
endforeach()
endforeach()
####################################################################################
###### nr_ulschsim unit test ######
####################################################################################
set(NR_ULSCHSIM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_ULSCHSIM_OPTION_TO_TEST_LIST
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_ULSCHSIM_OPTION_TO_TEST_LIST
xdma
)
endif()
set(test_nr_ulschsim_test1 "-R" "106" "-m9" "-s13" "-n100")
set(test_nr_ulschsim_test2 "-R" "217" "-m15" "-s15" "-n100")
set(test_nr_ulschsim_test3 "-R" "273" "-m19" "-s20" "-n100")
set(test_nr_ulschsim_test4 "-R" "106" "-m9" "-s13" "-n100" "-y4" "-z4" "-W4")
set(NR_ULSCHSIM_TEST_CASE_OPTION_LIST
test_nr_ulschsim_test1
test_nr_ulschsim_test2
test_nr_ulschsim_test3
test_nr_ulschsim_test4
)
foreach(NR_ULSCHSIM_OPTION_TO_TEST IN LISTS NR_ULSCHSIM_OPTION_TO_TEST_LIST)
foreach(NR_ULSCHSIM_TEST_CASE IN LISTS NR_ULSCHSIM_TEST_CASE_OPTION_LIST)
add_test(
NAME ${NR_ULSCHSIM_TEST_CASE}_${NR_ULSCHSIM_OPTION_TO_TEST}
COMMAND nr_ulschsim ${${NR_ULSCHSIM_TEST_CASE}} ${${NR_ULSCHSIM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
endforeach()
endforeach()
####################################################################################
###### nr_dlsim unit test ######
####################################################################################
set(t2_offload_nr_dlsim "-c" "-O" "${CMAKE_CURRENT_SOURCE_DIR}/t2_offload.conf")
set(NR_DLSIM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_DLSIM_OPTION_TO_TEST_LIST
t2_offload_nr_dlsim
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_DLSIM_OPTION_TO_TEST_LIST
xdma
)
endif()
set(test_nr_dlsim_basic_test1 "-n100" "-R106" "-b106" "-s5")
set(test_nr_dlsim_basic_test2 "-n100" "-R217" "-b217" "-s5")
set(test_nr_dlsim_basic_test3 "-n100" "-R273" "-b273" "-s5")
set(test_nr_dlsim_basic_test4 "-n100" "-s1" "-S2" "-t25")
set(test_nr_dlsim_basic_test5 "-n100" "-s1" "-S2" "-t33")
set(test_nr_dlsim_basic_test6 "-n100" "-s5" "-S7" "-t50")
set(test_nr_dlsim_basic_test7 "-n100" "-m0" "-e0" "-R25" "-b25" "-i" "2" "1" "0")
set(test_nr_dlsim_offset_test1 "-n100" "-R106" "-a25" "-s5")
set(test_nr_dlsim_offset_test2 "-n100" "-R106" "-a51" "-s5")
set(test_nr_dlsim_offset_test3 "-n100" "-R217" "-b100" "-s5")
set(test_nr_dlsim_offset_test4 "-n100" "-R217" "-a80" "-s5")
set(test_nr_dlsim_offset_test5 "-n100" "-R217" "-a110" "-s5" "-b100")
set(test_nr_dlsim_mcs_mimo_test1 "-n100" "-e27" "-s30")
set(test_nr_dlsim_mcs_mimo_test2 "-n100" "-e16" "-s11" "-S13")
set(test_nr_dlsim_mcs_mimo_test3 "-n100" "-q1" "-e26" "-s30")
set(test_nr_dlsim_mcs_mimo_test4 "-n100" "-e0 -t95" "-S-1.0" "-i" "2" "1" "0")
set(test_nr_dlsim_mcs_mimo_test5 "-n10" "-s20" "-U" "3" "0" "0" "2" "-gA" "-x1" "-y4" "-z4")
set(test_nr_dlsim_mcs_mimo_test6 "-n10" "-s20" "-U" "3" "0" "0" "2" "-gA" "-x2" "-y4" "-z4")
set(test_nr_dlsim_mcs_mimo_test7 "-n10" "-s20" "-U" "3" "0" "0" "2" "-x4" "-y4" "-z4")
set(test_nr_dlsim_dmrs_ptrs_test1 "-n100" "-s5" "-T" "2" "2" "2")
set(test_nr_dlsim_dmrs_ptrs_test2 "-n100" "-s5" "-T" "2" "1" "2")
set(test_nr_dlsim_dmrs_ptrs_test3 "-n100" "-s5" "-T" "2" "0" "4")
set(test_nr_dlsim_dmrs_ptrs_test4 "-n100" "-s5" "-S7" "-U" "2" "0" "1")
set(test_nr_dlsim_dmrs_ptrs_test5 "-n100" "-s5" "-S7" "-U" "2" "0" "2")
set(test_nr_dlsim_dmrs_ptrs_test6 "-n100" "-s5" "-S7" "-U" "2" "1" "3")
set(NR_DLSIM_TEST_CASE_OPTION_LIST
test_nr_dlsim_basic_test1
test_nr_dlsim_basic_test2
test_nr_dlsim_basic_test3
test_nr_dlsim_basic_test4
test_nr_dlsim_basic_test5
test_nr_dlsim_basic_test6
test_nr_dlsim_basic_test7
test_nr_dlsim_offset_test1
test_nr_dlsim_offset_test2
test_nr_dlsim_offset_test3
test_nr_dlsim_offset_test4
test_nr_dlsim_offset_test5
test_nr_dlsim_mcs_mimo_test1
test_nr_dlsim_mcs_mimo_test2
test_nr_dlsim_mcs_mimo_test3
test_nr_dlsim_mcs_mimo_test4
test_nr_dlsim_mcs_mimo_test5
test_nr_dlsim_mcs_mimo_test6
test_nr_dlsim_mcs_mimo_test7
test_nr_dlsim_dmrs_ptrs_test1
test_nr_dlsim_dmrs_ptrs_test2
test_nr_dlsim_dmrs_ptrs_test3
test_nr_dlsim_dmrs_ptrs_test4
test_nr_dlsim_dmrs_ptrs_test5
test_nr_dlsim_dmrs_ptrs_test6
)
foreach(NR_DLSIM_OPTION_TO_TEST IN LISTS NR_DLSIM_OPTION_TO_TEST_LIST)
foreach(NR_DLSIM_TEST_CASE IN LISTS NR_DLSIM_TEST_CASE_OPTION_LIST)
add_test(
NAME ${NR_DLSIM_TEST_CASE}_${NR_DLSIM_OPTION_TO_TEST}
COMMAND nr_dlsim -P ${${NR_DLSIM_TEST_CASE}} ${${NR_DLSIM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
set_property(
TEST ${NR_DLSIM_TEST_CASE}_${NR_DLSIM_OPTION_TO_TEST}
PROPERTY PASS_REGULAR_EXPRESSION "PDSCH test OK"
)
endforeach()
endforeach()
####################################################################################
###### nr_dlschsim unit test ######
####################################################################################
set(NR_DLSCHSIM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_DLSCHSIM_OPTION_TO_TEST_LIST
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_DLSCHSIM_OPTION_TO_TEST_LIST
xdma
)
endif()
set(test_nr_dlschsim_test1 "-R" "106" "-m9" "-s13" "-n100")
set(test_nr_dlschsim_test2 "-R" "217" "-m15" "-s15" "-n100")
set(test_nr_dlschsim_test3 "-R" "273" "-m19" "-s20" "-n100")
set(NR_DLSCHSIM_TEST_CASE_OPTION_LIST
test_nr_dlschsim_test1
test_nr_dlschsim_test2
test_nr_dlschsim_test3
)
foreach(NR_DLSCHSIM_OPTION_TO_TEST IN LISTS NR_DLSCHSIM_OPTION_TO_TEST_LIST)
foreach(NR_DLSCHSIM_TEST_CASE IN LISTS NR_DLSCHSIM_TEST_CASE_OPTION_LIST)
add_test(
NAME ${NR_DLSCHSIM_TEST_CASE}_${NR_DLSCHSIM_OPTION_TO_TEST}
COMMAND nr_dlschsim ${${NR_DLSCHSIM_TEST_CASE}} ${${NR_DLSCHSIM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
endforeach()
endforeach()
####################################################################################
###### nr-softmodem unit test ######
####################################################################################
set(default_ldpc "-O" "${CMAKE_CURRENT_SOURCE_DIR}/gnb.sa.band78.106prb.rfsim.2x2.conf")
set(slot_segment "-O" "${CMAKE_CURRENT_SOURCE_DIR}/gnb.sa.band78.106prb.rfsim.2x2.slot_segment.conf")
set(t2_offload "-O" "${CMAKE_CURRENT_SOURCE_DIR}/gnb.sa.band78.106prb.rfsim.2x2.t2_offload.conf" "--ldpc-offload-enable")
set(slot_t2 "-O" "${CMAKE_CURRENT_SOURCE_DIR}/gnb.sa.band78.106prb.rfsim.2x2.slot_t2.conf")
set(xdma "-O" "${CMAKE_CURRENT_SOURCE_DIR}/gnb.sa.band78.106prb.rfsim.2x2.xdma.conf")
set(NR_SOFTMODEM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_SOFTMODEM_OPTION_TO_TEST_LIST
t2_offload
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_SOFTMODEM_OPTION_TO_TEST_LIST
xdma
)
endif()
foreach(NR_SOFTMODEM_OPTION_TO_TEST IN LISTS NR_SOFTMODEM_OPTION_TO_TEST_LIST)
add_test(
NAME two_ues_rfsim_${NR_SOFTMODEM_OPTION_TO_TEST}
COMMAND ${CMAKE_CURRENT_SOURCE_DIR}/two_ues_rfsim.sh ${${NR_SOFTMODEM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
endforeach()
####################################################################################
###### nr-uesoftmodem unit test ######
####################################################################################
set(default_ldpc "-O" "${CMAKE_CURRENT_SOURCE_DIR}/nrue.uicc.1.conf")
set(slot_segment "-O" "${CMAKE_CURRENT_SOURCE_DIR}/nrue.uicc.1.slot_segment.conf")
set(t2_offload "-O" "${CMAKE_CURRENT_SOURCE_DIR}/nrue.uicc.1.t2_offload.conf" "--ldpc-offload-enable")
set(slot_t2 "-O" "${CMAKE_CURRENT_SOURCE_DIR}/nrue.uicc.1.slot_t2.conf")
set(xdma "-O" "${CMAKE_CURRENT_SOURCE_DIR}/nrue.uicc.1.xdma.conf")
set(NR_UESOFTMODEM_OPTION_TO_TEST_LIST
default_ldpc
slot_segment
)
if (ENABLE_LDPC_T2)
list(APPEND NR_UESOFTMODEM_OPTION_TO_TEST_LIST
t2_offload
slot_t2
)
endif()
if (ENABLE_LDPC_XDMA)
list(APPEND NR_UESOFTMODEM_OPTION_TO_TEST_LIST
xdma
)
endif()
foreach(NR_UESOFTMODEM_OPTION_TO_TEST IN LISTS NR_UESOFTMODEM_OPTION_TO_TEST_LIST)
add_test(
NAME ue_coding_rfsim_${NR_UESOFTMODEM_OPTION_TO_TEST}
COMMAND ${CMAKE_CURRENT_SOURCE_DIR}/ue_coding_rfsim.sh ${${NR_UESOFTMODEM_OPTION_TO_TEST}}
COMMAND_EXPAND_LISTS
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
endforeach()

View File

@@ -1,268 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};

View File

@@ -1,274 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};
loader : {
ldpc : {
shlibversion : "_slot_segment";
};
};

View File

@@ -1,279 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};
nrLDPC_coding_t2 : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};
loader : {
ldpc : {
shlibversion : "_slot_t2";
};
};

View File

@@ -1,278 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -1,273 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};
ldpc_offload : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};

View File

@@ -1,278 +0,0 @@
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1 }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 5;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312;
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ( { ipv4 = "172.21.6.5";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_NG_AMF = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.16.51/22";
GNB_INTERFACE_NAME_FOR_NGU = "enp193s0f0";
GNB_IPV4_ADDRESS_FOR_NGU = "172.21.16.51/22";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
dl_max_mcs = 16; # there are retransmissions if more
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 75;
eNB_instances = [0];
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "mgmt_addr=192.168.10.2,addr=192.168.10.2,clock_source=internal,time_source=internal"
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="info";
};
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -1,7 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}

View File

@@ -1,13 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
loader : {
ldpc : {
shlibversion : "_slot_demo";
};
};

View File

@@ -1,13 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
loader : {
ldpc : {
shlibversion : "_slot_segment";
};
};

View File

@@ -1,18 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
nrLDPC_coding_t2 : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};
loader : {
ldpc : {
shlibversion : "_slot_t2";
};
};

View File

@@ -1,17 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -1,12 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
ldpc_offload : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};

View File

@@ -1,17 +0,0 @@
uicc0 = {
imsi = "208990100001132";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -1,7 +0,0 @@
uicc0 = {
imsi = "208990100001133";
key = "fec86ba6eb707ed08905757b1bb44b8f";
opc= "C42449363BBAD02B66D16BC975D77CC1";
dnn= "oai";
nssai_sst=1;
}

View File

@@ -1,5 +0,0 @@
loader : {
ldpc : {
shlibversion : "_slot_segment";
};
};

View File

@@ -1,10 +0,0 @@
nrLDPC_coding_t2 : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};
loader : {
ldpc : {
shlibversion : "_slot_t2";
};
};

View File

@@ -1,9 +0,0 @@
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -1,4 +0,0 @@
ldpc_offload : {
dpdk_dev : "41:00.0";
dpdk_core_list : "14-15";
};

View File

@@ -1,92 +0,0 @@
#!/bin/bash
create_namespace() {
local ue_id=$1
local name="ue$ue_id"
echo "creating namespace for UE ID ${ue_id} name ${name}"
ip netns add $name
ip link add v-eth$ue_id type veth peer name v-ue$ue_id
ip link set v-ue$ue_id netns $name
BASE_IP=$((200+ue_id))
ip addr add 10.$BASE_IP.1.100/24 dev v-eth$ue_id
ip link set v-eth$ue_id up
iptables -t nat -A POSTROUTING -s 10.$BASE_IP.1.0/255.255.255.0 -o lo -j MASQUERADE
iptables -A FORWARD -i lo -o v-eth$ue_id -j ACCEPT
iptables -A FORWARD -o lo -i v-eth$ue_id -j ACCEPT
ip netns exec $name ip link set dev lo up
ip netns exec $name ip addr add 10.$BASE_IP.1.$ue_id/24 dev v-ue$ue_id
ip netns exec $name ip link set v-ue$ue_id up
}
delete_namespace() {
local ue_id=$1
local name="ue$ue_id"
echo "deleting namespace for UE ID ${ue_id} name ${name}"
ip link delete v-eth$ue_id
ip netns delete $name
}
usage () {
echo "$1 <gnb_args>"
}
prog_name=$(basename $0)
if [[ $(id -u) -ne 0 ]] ; then echo "Please run as root"; exit 1; fi
if [[ $# -eq 0 ]]; then echo "error: no parameters given"; usage $prog_name; exit 1; fi
# Write gNB arguments
GNB_ARGS=""
for arg in $@
do
GNB_ARGS="${GNB_ARGS} ${arg}"
done
# Launch gNB
./nr-softmodem --sa --rfsim --log_config.global_log_options level,nocolor,time$GNB_ARGS &
GNB_PID=$!
sleep 3
# Create 2 network namespaces
create_namespace 1
create_namespace 2
# Launch UE 1
ip netns exec ue1 ./nr-uesoftmodem --sa --rfsim -r 106 --numerology 1 --band 78 -C 3319680000 --ue-nb-ant-tx 2 --ue-nb-ant-rx 2 -O ../../../openair1/PHY/CODING/tests/nrue.uicc.1.conf --rfsimulator.serveraddr 10.201.1.100 &
UE1_PID=$!
sleep 3
# Launch UE 2
ip netns exec ue2 ./nr-uesoftmodem --sa --rfsim -r 106 --numerology 1 --band 78 -C 3319680000 --ue-nb-ant-tx 2 --ue-nb-ant-rx 2 -O ../../../openair1/PHY/CODING/tests/nrue.uicc.2.conf --rfsimulator.serveraddr 10.202.1.100 &
UE2_PID=$!
# Wait
sleep 9
# Test phase using ping
SUCCESS=0
ip netns exec ue1 ping -c 5 -i 0.1 -w 1 12.1.1.1
SUCCESS=$((${SUCCESS}+$?))
ip netns exec ue2 ping -c 5 -i 0.1 -w 1 12.1.1.1
SUCCESS=$((${SUCCESS}+$?))
# Stop UEs and gNB
# SIGINT
kill -2 ${UE1_PID}
kill -2 ${UE2_PID}
sleep 3
kill -2 ${GNB_PID}
sleep 3
# SIGKILL
kill -9 ${UE1_PID}
kill -9 ${UE2_PID}
kill -9 ${GNB_PID}
# Delete network namespaces
delete_namespace 1
delete_namespace 2
exit ${SUCCESS}

View File

@@ -1,80 +0,0 @@
#!/bin/bash
create_namespace() {
local ue_id=$1
local name="ue$ue_id"
echo "creating namespace for UE ID ${ue_id} name ${name}"
ip netns add $name
ip link add v-eth$ue_id type veth peer name v-ue$ue_id
ip link set v-ue$ue_id netns $name
BASE_IP=$((200+ue_id))
ip addr add 10.$BASE_IP.1.100/24 dev v-eth$ue_id
ip link set v-eth$ue_id up
iptables -t nat -A POSTROUTING -s 10.$BASE_IP.1.0/255.255.255.0 -o lo -j MASQUERADE
iptables -A FORWARD -i lo -o v-eth$ue_id -j ACCEPT
iptables -A FORWARD -o lo -i v-eth$ue_id -j ACCEPT
ip netns exec $name ip link set dev lo up
ip netns exec $name ip addr add 10.$BASE_IP.1.$ue_id/24 dev v-ue$ue_id
ip netns exec $name ip link set v-ue$ue_id up
}
delete_namespace() {
local ue_id=$1
local name="ue$ue_id"
echo "deleting namespace for UE ID ${ue_id} name ${name}"
ip link delete v-eth$ue_id
ip netns delete $name
}
usage () {
echo "$1 <ue_args>"
}
prog_name=$(basename $0)
if [[ $(id -u) -ne 0 ]] ; then echo "Please run as root"; exit 1; fi
if [[ $# -eq 0 ]]; then echo "error: no parameters given"; usage $prog_name; exit 1; fi
# Launch gNB
./nr-softmodem --sa --rfsim --log_config.global_log_options level,nocolor,time -O ../../../openair1/PHY/CODING/tests/gnb.sa.band78.106prb.rfsim.2x2.conf &
GNB_PID=$!
sleep 3
# Create 1 network namespaces
create_namespace 1
# Write UE arguments
UE_ARGS=""
for arg in $@
do
UE_ARGS="${UE_ARGS} ${arg}"
done
# Launch UE 1
ip netns exec ue1 ./nr-uesoftmodem --sa --rfsim -r 106 --numerology 1 --band 78 -C 3319680000 --ue-nb-ant-tx 2 --ue-nb-ant-rx 2 --rfsimulator.serveraddr 10.201.1.100 $UE_ARGS &
UE1_PID=$!
# Wait
sleep 9
# Test phase using ping
SUCCESS=0
ip netns exec ue1 ping -c 5 -i 0.1 -w 1 12.1.1.1
SUCCESS=$((${SUCCESS}+$?))
# Stop UEs and gNB
# SIGINT
kill -2 ${UE1_PID}
sleep 3
kill -2 ${GNB_PID}
sleep 3
# SIGKILL
kill -9 ${UE1_PID}
kill -9 ${GNB_PID}
# Delete network namespaces
delete_namespace 1
exit ${SUCCESS}

View File

@@ -1,9 +0,0 @@
nrLDPC_coding_xdma : {
num_threads_prepare : 2;
};
loader : {
ldpc : {
shlibversion : "_xdma";
};
};

View File

@@ -39,7 +39,7 @@ int phy_init_RU(RU_t *ru) {
RU_CALIBRATION *calibration = &ru->calibration;
int i,j,p,re;
//load_dftslib();
LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx);
LOG_D(PHY, "Initializing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
if (ru->is_slave == 1) {
generate_ul_ref_sigs_rx();
@@ -54,8 +54,11 @@ int phy_init_RU(RU_t *ru) {
for (i=0; i<ru->nb_tx; i++) {
// Allocate 10 subframes of I/Q TX signal data (time) if not
ru->common.txdata[i] = (int32_t *)malloc16_clear( fp->samples_per_tti*10*sizeof(int32_t) );
LOG_I(PHY,"[INIT] common.txdata[%d] = %p (%lu bytes)\n",i,ru->common.txdata[i],
fp->samples_per_tti*10*sizeof(int32_t));
LOG_D(PHY,
"[INIT] common.txdata[%d] = %p (%lu bytes)\n",
i,
ru->common.txdata[i],
fp->samples_per_tti * 10 * sizeof(int32_t));
}
if (ru->is_slave == 1) {
@@ -71,7 +74,6 @@ int phy_init_RU(RU_t *ru) {
}
} // IF5 or local RF
else {
// LOG_I(PHY,"No rxdata/txdata for RU\n");
ru->common.txdata = (int32_t **)NULL;
ru->common.rxdata = (int32_t **)NULL;
}
@@ -79,22 +81,21 @@ int phy_init_RU(RU_t *ru) {
if (ru->function != NGFI_RRU_IF5) { // we need to do RX/TX RU processing
load_dftslib();
init_7_5KHz();
LOG_I(PHY,"nb_tx %d\n",ru->nb_tx);
LOG_D(PHY, "nb_tx %d\n", ru->nb_tx);
ru->common.rxdata_7_5kHz = (int32_t **)malloc16(ru->nb_rx*sizeof(int32_t *) );
for (i=0; i<ru->nb_rx; i++) {
ru->common.rxdata_7_5kHz[i] = (int32_t *)malloc16_clear( 2*fp->samples_per_tti*2*sizeof(int32_t) );
LOG_I(PHY,"rxdata_7_5kHz[%d] %p for RU %d\n",i,ru->common.rxdata_7_5kHz[i],ru->idx);
LOG_D(PHY, "rxdata_7_5kHz[%d] %p for RU %d\n", i, ru->common.rxdata_7_5kHz[i], ru->idx);
}
// allocate IFFT input buffers (TX)
ru->common.txdataF_BF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t *));
LOG_I(PHY,"[INIT] common.txdata_BF= %p (%lu bytes)\n",ru->common.txdataF_BF,
ru->nb_tx*sizeof(int32_t *));
LOG_D(PHY, "[INIT] common.txdata_BF= %p (%lu bytes)\n", ru->common.txdataF_BF, ru->nb_tx * sizeof(int32_t *));
for (i=0; i<ru->nb_tx; i++) {
ru->common.txdataF_BF[i] = (int32_t *)malloc16_clear(fp->symbols_per_tti*fp->ofdm_symbol_size*sizeof(int32_t) );
LOG_I(PHY,"txdataF_BF[%d] %p for RU %d\n",i,ru->common.txdataF_BF[i],ru->idx);
LOG_D(PHY, "txdataF_BF[%d] %p for RU %d\n", i, ru->common.txdataF_BF[i], ru->idx);
}
// allocate FFT output buffers (RX)
@@ -103,7 +104,7 @@ int phy_init_RU(RU_t *ru) {
for (i=0; i<ru->nb_rx; i++) {
// allocate 2 subframes of I/Q signal data (frequency)
ru->common.rxdataF[i] = (int32_t *)malloc16_clear(sizeof(int32_t)*(2*fp->ofdm_symbol_size*fp->symbols_per_tti) );
LOG_I(PHY,"rxdataF[%d] %p for RU %d\n",i,ru->common.rxdataF[i],ru->idx);
LOG_D(PHY, "rxdataF[%d] %p for RU %d\n", i, ru->common.rxdataF[i], ru->idx);
}
if (ru->is_slave == 1) {
@@ -114,7 +115,7 @@ int phy_init_RU(RU_t *ru) {
for (i=0; i<ru->nb_rx; i++) {
// allocate 2 subframes of I/Q signal data (frequency)
calibration->rxdataF_ext[i] = (int32_t *)malloc16_clear(sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
LOG_I(PHY,"rxdataF_ext[%d] %p for RU %d\n",i,calibration->rxdataF_ext[i],ru->idx);
LOG_D(PHY, "rxdataF_ext[%d] %p for RU %d\n", i, calibration->rxdataF_ext[i], ru->idx);
calibration->drs_ch_estimates[i] = (int32_t *)malloc16_clear(sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti);
}
}
@@ -186,7 +187,7 @@ int phy_init_RU(RU_t *ru) {
void phy_free_RU(RU_t *ru) {
int i,j,p;
RU_CALIBRATION *calibration = &ru->calibration;
LOG_I(PHY, "Freeing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
LOG_D(PHY, "Freeing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so free memory for time-domain signals
for (i = 0; i < ru->nb_tx; i++) free_and_zero(ru->common.txdata[i]);

View File

@@ -26,7 +26,6 @@
#include "PHY/defs_gNB.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "PHY/INIT/nr_phy_init.h"
#include "PHY/CODING/nrLDPC_coding/nrLDPC_coding_interface.h"
#include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
@@ -41,7 +40,6 @@
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "SCHED_NR/fapi_nr_l1.h"
#include "PHY/NR_REFSIG/ul_ref_seq_nr.h"
#include <string.h>
int l1_north_init_gNB() {
@@ -49,19 +47,19 @@ int l1_north_init_gNB() {
AssertFatal(RC.nb_nr_L1_inst>0,"nb_nr_L1_inst=%d\n",RC.nb_nr_L1_inst);
AssertFatal(RC.gNB!=NULL,"RC.gNB is null\n");
LOG_I(PHY,"%s() RC.nb_nr_L1_inst:%d\n", __FUNCTION__, RC.nb_nr_L1_inst);
LOG_D(PHY, "%s() RC.nb_nr_L1_inst:%d\n", __FUNCTION__, RC.nb_nr_L1_inst);
for (int i=0; i<RC.nb_nr_L1_inst; i++) {
AssertFatal(RC.gNB[i]!=NULL,"RC.gNB[%d] is null\n",i);
if ((RC.gNB[i]->if_inst = NR_IF_Module_init(i))<0) return(-1);
LOG_I(PHY,"%s() RC.gNB[%d] installing callbacks\n", __FUNCTION__, i);
LOG_D(PHY, "%s() RC.gNB[%d] installing callbacks\n", __FUNCTION__, i);
RC.gNB[i]->if_inst->NR_PHY_config_req = nr_phy_config_request;
RC.gNB[i]->if_inst->NR_Schedule_response = nr_schedule_response;
}
} else {
LOG_I(PHY,"%s() Not installing PHY callbacks - RC.nb_nr_L1_inst:%d RC.gNB:%p\n", __FUNCTION__, RC.nb_nr_L1_inst, RC.gNB);
LOG_D(PHY, "%s() Not installing PHY callbacks - RC.nb_nr_L1_inst:%d RC.gNB:%p\n", __FUNCTION__, RC.nb_nr_L1_inst, RC.gNB);
}
return(0);
@@ -104,7 +102,6 @@ void reset_active_stats(PHY_VARS_gNB *gNB, int frame)
// A global var to reduce the changes size
ldpc_interface_t ldpc_interface = {0}, ldpc_interface_offload = {0};
nrLDPC_coding_interface_t nrLDPC_coding_interface = {0};
void phy_init_nr_gNB(PHY_VARS_gNB *gNB)
{
@@ -128,7 +125,7 @@ void phy_init_nr_gNB(PHY_VARS_gNB *gNB)
AssertFatal(Ptx > 0 && Ptx < 9,"Ptx %d is not supported\n", Ptx);
AssertFatal(Prx > 0 && Prx < 9,"Prx %d is not supported\n", Prx);
LOG_I(PHY, "[gNB %d]About to wait for gNB to be configured\n", gNB->Mod_id);
LOG_D(PHY, "[gNB %d]About to wait for gNB to be configured\n", gNB->Mod_id);
while(gNB->configured == 0)
usleep(10000);
@@ -141,18 +138,15 @@ void phy_init_nr_gNB(PHY_VARS_gNB *gNB)
nr_init_fde(); // Init array for frequency equalization of transform precoding of PUSCH
gNB->nrLDPC_coding_interface_flag = 0;
int ret_loader = load_nrLDPC_coding_interface(NULL, &nrLDPC_coding_interface);
if (ret_loader >= 0) {
gNB->nrLDPC_coding_interface_flag = 1;
} else {
load_LDPClib(NULL, &ldpc_interface);
if (gNB->ldpc_offload_flag)
load_LDPClib("_t2", &ldpc_interface_offload);
}
load_LDPClib(NULL, &ldpc_interface);
pthread_mutex_init(&gNB->UL_INFO.crc_rx_mutex, NULL);
if (gNB->ldpc_offload_flag)
load_LDPClib("_t2", &ldpc_interface_offload);
else
load_LDPClib(NULL, &ldpc_interface);
gNB->max_nb_pdsch = MAX_MOBILES_PER_GNB;
init_delay_table(fp->ofdm_symbol_size, MAX_DELAY_COMP, NR_MAX_OFDM_SYMBOL_SIZE, fp->delay_table);
@@ -387,8 +381,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
init_symbol_rotation(fp);
init_timeshift_rotation(fp);
gNB->configured = 1;
LOG_I(PHY,"gNB configured\n");
gNB->configured = 1;
}
void nr_phy_config_request(NR_PHY_Config_t *phy_config)
@@ -412,7 +405,7 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config)
LOG_I(PHY, "DL frequency %lu Hz, UL frequency %lu Hz: band %d, uldl offset %d Hz\n", fp->dl_CarrierFreq, fp->ul_CarrierFreq, fp->nr_band, dlul_offset);
fp->threequarter_fs = get_softmodem_params()->threequarter_fs;
LOG_A(PHY,"Configuring MIB for instance %d, : (Nid_cell %d,DL freq %llu, UL freq %llu)\n",
LOG_D(PHY,"Configuring MIB for instance %d, : (Nid_cell %d,DL freq %llu, UL freq %llu)\n",
Mod_id,
gNB_config->cell_config.phy_cell_id.value,
(unsigned long long)fp->dl_CarrierFreq,
@@ -440,8 +433,6 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config)
fp->ofdm_offset_divisor = RC.gNB[Mod_id]->ofdm_offset_divisor;
init_symbol_rotation(fp);
init_timeshift_rotation(fp);
LOG_I(PHY,"gNB %d configured\n",Mod_id);
}
void init_DLSCH_struct(PHY_VARS_gNB *gNB, processingData_L1tx_t *msg)
@@ -482,7 +473,6 @@ void init_nr_transport(PHY_VARS_gNB *gNB)
NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
const nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config;
LOG_I(PHY, "Initialise nr transport\n");
int nb_slots_per_period = cfg->cell_config.frame_duplex_type.value ?
fp->slots_per_frame / get_nb_periods_per_frame(cfg->tdd_table.tdd_period.value) :

View File

@@ -33,7 +33,7 @@ int nr_phy_init_RU(RU_t *ru)
{
NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms;
LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d, nb_rx %d\n",ru_if_types[ru->if_south],ru->nb_tx, ru->nb_rx);
LOG_D(PHY, "Initializing RU signal buffers (if_south %s) nb_tx %d, nb_rx %d\n", ru_if_types[ru->if_south], ru->nb_tx, ru->nb_rx);
nfapi_nr_config_request_scf_t *cfg = &ru->config;
ru->nb_log_antennas = 0;
@@ -60,29 +60,30 @@ int nr_phy_init_RU(RU_t *ru)
for (int i = 0; i < ru->nb_tx; i++) {
// Allocate 10 subframes of I/Q TX signal data (time) if not
ru->common.txdata[i] = (int32_t*)malloc16_clear((ru->sf_extension + fp->samples_per_frame)*sizeof(int32_t));
LOG_I(PHY,"[INIT] common.txdata[%d] = %p (%lu bytes,sf_extension %d)\n",i,ru->common.txdata[i],
(ru->sf_extension + fp->samples_per_frame)*sizeof(int32_t),ru->sf_extension);
LOG_D(PHY,
"[INIT] common.txdata[%d] = %p (%lu bytes,sf_extension %d)\n",
i,
ru->common.txdata[i],
(ru->sf_extension + fp->samples_per_frame) * sizeof(int32_t),
ru->sf_extension);
ru->common.txdata[i] = &ru->common.txdata[i][ru->sf_extension];
LOG_I(PHY,"[INIT] common.txdata[%d] = %p \n",i,ru->common.txdata[i]);
LOG_D(PHY, "[INIT] common.txdata[%d] = %p \n", i, ru->common.txdata[i]);
}
for (int i = 0; i < ru->nb_rx; i++) {
ru->common.rxdata[i] = (int32_t*)malloc16_clear( fp->samples_per_frame*sizeof(int32_t) );
}
} // IF5 or local RF
else {
// LOG_I(PHY,"No rxdata/txdata for RU\n");
ru->common.txdata = (int32_t**)NULL;
ru->common.rxdata = (int32_t**)NULL;
}
if (ru->function != NGFI_RRU_IF5) { // we need to do RX/TX RU processing
LOG_I(PHY,"nb_tx %d\n",ru->nb_tx);
LOG_D(PHY, "nb_tx %d\n", ru->nb_tx);
ru->common.rxdata_7_5kHz = (int32_t**)malloc16(ru->nb_rx*sizeof(int32_t*) );
for (int i = 0; i < ru->nb_rx; i++) {
ru->common.rxdata_7_5kHz[i] = (int32_t*)malloc16_clear( 2*fp->samples_per_subframe*2*sizeof(int32_t) );
LOG_I(PHY,"rxdata_7_5kHz[%d] %p for RU %d\n",i,ru->common.rxdata_7_5kHz[i],ru->idx);
LOG_D(PHY, "rxdata_7_5kHz[%d] %p for RU %d\n", i, ru->common.rxdata_7_5kHz[i], ru->idx);
}
@@ -94,10 +95,10 @@ int nr_phy_init_RU(RU_t *ru)
// allocate IFFT input buffers (TX)
ru->common.txdataF_BF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*));
LOG_I(PHY,"[INIT] common.txdata_BF= %p (%lu bytes)\n", ru->common.txdataF_BF, ru->nb_tx*sizeof(int32_t*));
LOG_D(PHY, "[INIT] common.txdata_BF= %p (%lu bytes)\n", ru->common.txdataF_BF, ru->nb_tx * sizeof(int32_t *));
for (int i = 0; i < ru->nb_tx; i++) {
ru->common.txdataF_BF[i] = (int32_t*)malloc16_clear(fp->samples_per_subframe_wCP*sizeof(int32_t) );
LOG_I(PHY,"txdataF_BF[%d] %p for RU %d\n",i,ru->common.txdataF_BF[i],ru->idx);
LOG_D(PHY, "txdataF_BF[%d] %p for RU %d\n", i, ru->common.txdataF_BF[i], ru->idx);
}
// allocate FFT output buffers (RX)
ru->common.rxdataF = (int32_t**)malloc16(ru->nb_rx*sizeof(int32_t*) );
@@ -105,7 +106,7 @@ int nr_phy_init_RU(RU_t *ru)
// allocate 4 slots of I/Q signal data (frequency)
int size = RU_RX_SLOT_DEPTH * fp->symbols_per_slot * fp->ofdm_symbol_size;
ru->common.rxdataF[i] = (int32_t*)malloc16_clear(sizeof(**ru->common.rxdataF) * size);
LOG_I(PHY,"rxdataF[%d] %p for RU %d\n",i,ru->common.rxdataF[i],ru->idx);
LOG_D(PHY, "rxdataF[%d] %p for RU %d\n", i, ru->common.rxdataF[i], ru->idx);
}
/* number of elements of an array X is computed as sizeof(X) / sizeof(X[0]) */
@@ -124,7 +125,7 @@ int nr_phy_init_RU(RU_t *ru)
AssertFatal(ru->num_gNB <= NUMBER_OF_gNB_MAX,"gNB instances %d > %d\n",
ru->num_gNB,NUMBER_OF_gNB_MAX);
LOG_I(PHY,"[INIT] %s() ru->num_gNB:%d \n", __FUNCTION__, ru->num_gNB);
LOG_D(PHY, "[INIT] %s() ru->num_gNB:%d \n", __FUNCTION__, ru->num_gNB);
} // !=IF5
@@ -135,7 +136,7 @@ int nr_phy_init_RU(RU_t *ru)
void nr_phy_free_RU(RU_t *ru)
{
LOG_I(PHY, "Freeing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
LOG_D(PHY, "Freeing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so free memory for time-domain signals
// Hack: undo what is done at allocation

View File

@@ -53,28 +53,23 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms,
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
// do ifft of channel estimate
int len=0;
switch(frame_parms->N_RB_DL) {
case 6:
dft(DFT_128,(int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
(int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
1);
break;
len = 128;
break;
case 25:
dft(DFT_512,(int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
(int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
1);
break;
len = 512;
break;
case 50:
dft(DFT_1024,(int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
(int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
1);
break;
len = 1024;
break;
case 100:
dft(DFT_2048,(int16_t*) &lte_eNB_srs->srs_ch_estimates[aa][0],
(int16_t*) lte_eNB_srs->srs_ch_estimates_time[aa],
1);
break;
len = 2048;
break;
}
if (len)
dft(get_dft(len), (int16_t *)lte_eNB_srs->srs_ch_estimates[aa], (int16_t *)lte_eNB_srs->srs_ch_estimates_time[aa], 1);
#ifdef DEBUG_PHY
sprintf(fname,"srs_ch_estimates_time_%d%d.m",ind,aa);
sprintf(vname,"srs_time_%d%d",ind,aa);

View File

@@ -47,9 +47,10 @@ int lte_dl_channel_estimation(PHY_VARS_UE *ue,
uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t nushift,pilot0,pilot1,pilot2,pilot3;
uint8_t previous_thread_id = ue->current_thread_id[Ns>>1]==0 ? (RX_NB_TH-1):(ue->current_thread_id[Ns>>1]-1);
int **dl_ch_estimates =ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset];
LTE_UE_COMMON_PER_THREAD * vars=&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]];
int **dl_ch_estimates =vars->dl_ch_estimates[eNB_offset];
int **dl_ch_estimates_previous=ue->common_vars.common_vars_rx_data_per_thread[previous_thread_id].dl_ch_estimates[eNB_offset];
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF;
int **rxdataF=vars->rxdataF;
pilot0 = 0;
if (ue->frame_parms.Ncp == 0) { // normal prefix
@@ -657,53 +658,27 @@ int lte_dl_channel_estimation(PHY_VARS_UE *ue,
}
}
idft_size_idx_t idftsizeidx;
switch (ue->frame_parms.ofdm_symbol_size) {
case 128:
idftsizeidx = IDFT_128;
break;
case 256:
idftsizeidx = IDFT_256;
break;
case 512:
idftsizeidx = IDFT_512;
break;
case 1024:
idftsizeidx = IDFT_1024;
break;
case 1536:
idftsizeidx = IDFT_1536;
break;
case 2048:
idftsizeidx = IDFT_2048;
break;
default:
idftsizeidx = IDFT_512;
break;
}
int s = ue->frame_parms.ofdm_symbol_size;
if (s != 128 && s != 256 && s != 512 && s != 1024 && s != 1536 && s != 2048)
s = 512;
if( ((Ns%2) == 0) && (l == pilot0)) {
// do ifft of channel estimate
for (aarx=0; aarx<ue->frame_parms.nb_antennas_rx; aarx++)
for (p=0; p<ue->frame_parms.nb_antenna_ports_eNB; p++) {
if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx]) {
if (dl_ch_estimates[(p<<1)+aarx]) {
//LOG_I(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d \n", Ns, ue->current_thread_id[Ns>>1], l);
idft(idftsizeidx,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates_time[eNB_offset][(p<<1)+aarx],1);
idft(get_idft(s),
(int16_t *)&dl_ch_estimates[(p << 1) + aarx][8],
(int16_t *)vars->dl_ch_estimates_time[eNB_offset][(p << 1) + aarx],
1);
}
}
}
T(T_UE_PHY_DL_CHANNEL_ESTIMATE, T_INT(eNB_id), T_INT(0),
T_INT(ue->proc.proc_rxtx[ue->current_thread_id[Ns>>1]].frame_rx%1024), T_INT(ue->proc.proc_rxtx[ue->current_thread_id[Ns>>1]].subframe_rx),
T_INT(0), T_BUFFER(&ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates_time[eNB_offset][0][0], 512 * 4));
T_INT(0), T_BUFFER(&vars->dl_ch_estimates_time[eNB_offset][0][0], 512 * 4));
return(0);
}

View File

@@ -721,44 +721,37 @@ int lte_dl_mbsfn_channel_estimation(PHY_VARS_UE *ue,
// do ifft of channel estimate
for (aa=0; aa<ue->frame_parms.nb_antennas_rx*ue->frame_parms.nb_antennas_tx; aa++) {
if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa]) {
int32_t *tmp = ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa];
if (tmp) {
int len;
switch (ue->frame_parms.N_RB_DL) {
case 6:
idft(IDFT_128,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa],
1);
len = 128;
break;
case 25:
idft(IDFT_512,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa],
1);
len = 512;
break;
case 50:
idft(IDFT_1024,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa],
1);
len = 1024;
break;
case 75:
idft(IDFT_1536,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa],
1);
len=1536;
break;
case 100:
idft(IDFT_2048,(int16_t *) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_offset][aa][8],
(int16_t *) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[eNB_offset][aa],
1);
len = 2048;
break;
default:
break;
LOG_E(PHY, "Unknown N_RB_DL %d\n", ue->frame_parms.N_RB_DL);
return -1;
}
idft(get_idft(len),
(int16_t *)&tmp[8],
(int16_t *)ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]]
.dl_ch_estimates_time[eNB_offset][aa],
1);
}
}
return(0);
}
@@ -907,30 +900,27 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
// do ifft of channel estimate
for (aa=0; aa<ue->frame_parms.nb_antennas_rx*ue->frame_parms.nb_antennas_tx; aa++) {
if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa]) {
int32_t *tmp = ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa];
if (tmp) {
int len = 0;
switch (ue->frame_parms.N_RB_DL) {
case 25:
idft(IDFT_6144,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
(int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
1);
break;
case 50:
idft(IDFT_12288,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
(int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
1);
break;
case 100:
idft(IDFT_24576,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
(int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
1);
break;
default:
break;
case 25:
len = 6144;
break;
case 50:
len = 12288;
break;
case 100:
len = 24576;
break;
}
if (len)
idft(get_idft(len),
(int16_t *)&tmp[8],
(int16_t *)ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
1);
}
}
return(0);
}

View File

@@ -37,33 +37,29 @@
static c16_t *primary_synch_time[3] __attribute__((aligned(32)));
static void doIdft(int size, short *in, short *out) {
int len;
switch (size) {
case 6:
idft(IDFT_128,in,out,1);
break;
case 25:
idft(IDFT_512,in,out,1);
break;
case 50:
idft(IDFT_1024,in,out,1);
break;
case 75:
idft(IDFT_1536,in,out,1);
break;
case 100:
idft(IDFT_2048,in,out,1);
break;
default:
LOG_E(PHY,"Unsupported N_RB_DL %d\n",size);
abort();
break;
}
case 6:
len = 128;
break;
case 25:
len = 512;
break;
case 50:
len = 1024;
break;
case 75:
len=1536;
break;
case 100:
len = 2048;
break;
default:
LOG_E(PHY, "Unknown N_RB_DL %d\n", size);
return;
}
idft(get_idft(len), in, out, 1);
}
static void copyPrimary( c16_t *out, struct complex16 *in, int ofdmSize) {
int k=ofdmSize-36;
@@ -187,43 +183,29 @@ int ru_sync_time_init(RU_t *ru) { // LTE_UE_COMMON *common_vars
0,
ru->frame_parms->N_RB_DL,
0);
int len;
switch (ru->frame_parms->N_RB_DL) {
case 6:
idft(IDFT_128,(int16_t *)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]),
ru->dmrssync, /// complex output
1);
len = 128;
break;
case 25:
idft(IDFT_512,(int16_t *)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]),
ru->dmrssync, /// complex output
1);
len = 512;
break;
case 50:
idft(IDFT_1024,(int16_t *)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]),
ru->dmrssync, /// complex output
1);
len = 1024;
break;
case 75:
idft(IDFT_1536,(int16_t *)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]),
ru->dmrssync,
1); /// complex output
len = 1536;
break;
case 100:
idft(IDFT_2048,(int16_t *)(&dmrsp[0][3*ru->frame_parms->ofdm_symbol_size]),
ru->dmrssync, /// complex output
1);
len = 2048;
break;
default:
AssertFatal(1==0,"Unsupported N_RB_DL %d\n",ru->frame_parms->N_RB_DL);
break;
LOG_E(PHY, "Unknown N_RB_DL %d\n", ru->frame_parms->N_RB_DL);
return -1;
}
idft(get_idft(len), (int16_t *)&dmrsp[0][3 * ru->frame_parms->ofdm_symbol_size], ru->dmrssync,
1); /// complex output
return(0);
}

View File

@@ -222,33 +222,25 @@ int32_t lte_ul_channel_estimation(LTE_DL_FRAME_PARMS *frame_parms,
for(i=0; i<Msc_RS; i++)
((int32_t *)temp_in_ifft_0)[i] = ul_ch_estimates[aa][symbol_offset+i];
int len;
switch(frame_parms->N_RB_DL) {
case 6:
idft(IDFT_128,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 128;
break;
case 25:
idft(IDFT_512,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 512;
break;
case 50:
idft(IDFT_1024,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 1024;
break;
case 100:
idft(IDFT_2048,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 2048;
break;
default:
LOG_E(PHY, "Unknown N_RB_DL %d\n", frame_parms->N_RB_DL);
return -1;
}
idft(get_idft(len), (int16_t *)temp_in_ifft_0, (int16_t *)ul_ch_estimates_time[aa], 1);
#if T_TRACER
if (aa == 0)
@@ -501,33 +493,25 @@ int32_t lte_ul_channel_estimation_RRU(LTE_DL_FRAME_PARMS *frame_parms,
for(i=0; i<Msc_RS; i++)
((int32_t *)temp_in_ifft_0)[i] = ul_ch_estimates[aa][symbol_offset+i];
int len;
switch(frame_parms->N_RB_DL) {
case 6:
idft(IDFT_128,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 128;
break;
case 25:
idft(IDFT_512,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 512;
break;
case 50:
idft(IDFT_1024,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 1024;
break;
case 100:
idft(IDFT_2048,(int16_t *) temp_in_ifft_0,
(int16_t *) ul_ch_estimates_time[aa],
1);
len = 2048;
break;
default:
LOG_E(PHY, "Unknown N_RB_DL %d\n", frame_parms->N_RB_DL);
return -1;
}
idft(get_idft(len), (int16_t *)temp_in_ifft_0, (int16_t *)ul_ch_estimates_time[aa], 1);
#if T_TRACER
if (aa == 0)

View File

@@ -86,14 +86,17 @@ int find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type) {
AssertFatal(eNB!=NULL,"eNB is null\n");
for (int i=0; i<NUMBER_OF_ULSCH_MAX; i++) {
if (eNB->ulsch[i]==NULL) continue;
if (eNB->ulsch[i] == NULL)
continue;
if (type == SEARCH_EXIST_RA) {
if (eNB->ulsch[i]->rnti == rnti) return i;
if (eNB->ulsch[i]->rnti == rnti)
return i;
} else {
if ((eNB->ulsch[i]->harq_mask >0) &&
(eNB->ulsch[i]->rnti==rnti)) return i;
else if ((eNB->ulsch[i]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
if (eNB->ulsch[i]->harq_mask > 0 && eNB->ulsch[i]->rnti == rnti)
return i;
else if (eNB->ulsch[i]->harq_mask == 0 && first_free_index == -1)
first_free_index = i;
}
}
@@ -1963,7 +1966,7 @@ void fill_dci0(PHY_VARS_eNB *eNB,int frame,int subframe,L1_rxtx_proc_t *proc,
if(frame_parms->frame_type == TDD) {
UE_id = find_ulsch(pdu->dci_pdu_rel8.rnti, eNB,SEARCH_EXIST_OR_FREE);
if(UE_id >=0 || UE_id < NUMBER_OF_ULSCH_MAX) {
if (UE_id >= 0) {
eNB->ulsch[UE_id]->harq_processes[pdu->dci_pdu_rel8.harq_pid]->V_UL_DAI = dai +1;
}
}

View File

@@ -160,8 +160,12 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,
for (i=0; i<Mdlharq; i++) {
dlsch->harq_processes[i] = (LTE_DL_eNB_HARQ_t *)malloc16(sizeof(LTE_DL_eNB_HARQ_t));
LOG_I(PHY, "Required DLSCH mem size %d (bw scaling %d), dlsch->harq_processes[%d] %p\n",
MAX_DLSCH_PAYLOAD_BYTES/bw_scaling,bw_scaling, i,dlsch->harq_processes[i]);
LOG_D(PHY,
"Required DLSCH mem size %d (bw scaling %d), dlsch->harq_processes[%d] %p\n",
MAX_DLSCH_PAYLOAD_BYTES / bw_scaling,
bw_scaling,
i,
dlsch->harq_processes[i]);
if (dlsch->harq_processes[i]) {
bzero(dlsch->harq_processes[i],sizeof(LTE_DL_eNB_HARQ_t));

View File

@@ -292,104 +292,38 @@ void rx_prach0(PHY_VARS_eNB *eNB,
// do DFT
switch (fp->N_RB_UL) {
case 6:
if (prach_fmt == 4) {
dft(DFT_256,prach2,rxsigF[aa],1);
fft_size=256;
} else {
dft(DFT_1536,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1);
fft_size=1536;
}
fft_size = prach_fmt == 4 ? 256 : 1536;
break;
case 15:
if (prach_fmt == 4) {
dft(DFT_256,prach2,rxsigF[aa],1);
fft_size=256;
} else {
dft(DFT_3072,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1);
}
fft_size=3072;
fft_size = prach_fmt == 4 ? 256 : 3072;
break;
case 25:
default:
if (prach_fmt == 4) {
dft(DFT_1024,prach2,rxsigF[aa],1);
fft_size = 1024;
} else {
dft(DFT_6144,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_6144,prach2+12288,rxsigF[aa]+12288,1);
fft_size = 6144;
}
fft_size = prach_fmt == 4 ? 1024 : 6144;
break;
case 50:
if (prach_fmt == 4) {
dft(DFT_2048,prach2,rxsigF[aa],1);
fft_size=2048;
} else {
dft(DFT_12288,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_12288,prach2+24576,rxsigF[aa]+24576,1);
fft_size=12288;
}
fft_size = prach_fmt == 4 ? 2048 : 12288;
break;
case 75:
if (prach_fmt == 4) {
dft(DFT_3072,prach2,rxsigF[aa],1);
fft_size=3072;
} else {
dft(DFT_18432,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_18432,prach2+36864,rxsigF[aa]+36864,1);
fft_size=18432;
}
fft_size = prach_fmt == 4 ? 3072 : 18432;
break;
case 100:
if (fp->threequarter_fs==0) {
if (prach_fmt == 4) {
dft(DFT_4096,prach2,rxsigF[aa],1);
fft_size=2048;
} else {
dft(DFT_24576,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_24576,prach2+49152,rxsigF[aa]+49152,1);
fft_size=24576;
}
} else {
if (prach_fmt == 4) {
dft(DFT_3072,prach2,rxsigF[aa],1);
fft_size=3072;
} else {
dft(DFT_18432,prach2,rxsigF[aa],1);
if (prach_fmt>1)
dft(DFT_18432,prach2+36864,rxsigF[aa]+36864,1);
fft_size=18432;
}
}
if (fp->threequarter_fs == 0)
fft_size = prach_fmt == 4 ? 4096 : 24576;
else
fft_size = prach_fmt == 4 ? 3072 : 18432;
break;
}
dft(get_dft(fft_size), prach2, rxsigF[aa], 1);
if (prach_fmt > 1 && prach_fmt != 4)
dft(get_dft(fft_size), prach2 + 2 * fft_size, rxsigF[aa] + 2 * fft_size, 1);
k = (12*n_ra_prb) - 6*fp->N_RB_UL;
if (k<0) {

View File

@@ -1121,8 +1121,6 @@ void dump_ulsch_stats(FILE *fd,PHY_VARS_eNB *eNB,int frame) {
}
void clear_ulsch_stats(PHY_VARS_eNB *eNB) {
for (int i=0;i<NUMBER_OF_ULSCH_MAX;i++)
memset((void*)&eNB->ulsch_stats[i],0,sizeof(eNB->ulsch_stats[i]));
memset(eNB->ulsch_stats, 0, sizeof(eNB->ulsch_stats));
}

View File

@@ -127,12 +127,12 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) {
((uint32_t *)idft_in2)[ip+3] = z11[i];
}
}
dft_size_idx_t dftsize = get_dft(Msc_PUSCH);
switch (Msc_PUSCH) {
case 12:
dft(DFT_12,(int16_t *)idft_in0,(int16_t *)idft_out0,0);
dft(DFT_12,(int16_t *)idft_in1,(int16_t *)idft_out1,0);
dft(DFT_12,(int16_t *)idft_in2,(int16_t *)idft_out2,0);
dft(dftsize, (int16_t *)idft_in0, (int16_t *)idft_out0, 0);
dft(dftsize, (int16_t *)idft_in1, (int16_t *)idft_out1, 0);
dft(dftsize, (int16_t *)idft_in2, (int16_t *)idft_out2, 0);
norm128 = simde_mm_set1_epi16(9459);
for (i=0; i<12; i++) {
@@ -143,208 +143,10 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) {
break;
case 24:
dft(DFT_24,idft_in0,idft_out0,1);
dft(DFT_24,idft_in1,idft_out1,1);
dft(DFT_24,idft_in2,idft_out2,1);
break;
case 36:
dft(DFT_36,idft_in0,idft_out0,1);
dft(DFT_36,idft_in1,idft_out1,1);
dft(DFT_36,idft_in2,idft_out2,1);
break;
case 48:
dft(DFT_48,idft_in0,idft_out0,1);
dft(DFT_48,idft_in1,idft_out1,1);
dft(DFT_48,idft_in2,idft_out2,1);
break;
case 60:
dft(DFT_60,idft_in0,idft_out0,1);
dft(DFT_60,idft_in1,idft_out1,1);
dft(DFT_60,idft_in2,idft_out2,1);
break;
case 72:
dft(DFT_72,idft_in0,idft_out0,1);
dft(DFT_72,idft_in1,idft_out1,1);
dft(DFT_72,idft_in2,idft_out2,1);
break;
case 96:
dft(DFT_96,idft_in0,idft_out0,1);
dft(DFT_96,idft_in1,idft_out1,1);
dft(DFT_96,idft_in2,idft_out2,1);
break;
case 108:
dft(DFT_108,idft_in0,idft_out0,1);
dft(DFT_108,idft_in1,idft_out1,1);
dft(DFT_108,idft_in2,idft_out2,1);
break;
case 120:
dft(DFT_120,idft_in0,idft_out0,1);
dft(DFT_120,idft_in1,idft_out1,1);
dft(DFT_120,idft_in2,idft_out2,1);
break;
case 144:
dft(DFT_144,idft_in0,idft_out0,1);
dft(DFT_144,idft_in1,idft_out1,1);
dft(DFT_144,idft_in2,idft_out2,1);
break;
case 180:
dft(DFT_180,idft_in0,idft_out0,1);
dft(DFT_180,idft_in1,idft_out1,1);
dft(DFT_180,idft_in2,idft_out2,1);
break;
case 192:
dft(DFT_192,idft_in0,idft_out0,1);
dft(DFT_192,idft_in1,idft_out1,1);
dft(DFT_192,idft_in2,idft_out2,1);
break;
case 216:
dft(DFT_216,idft_in0,idft_out0,1);
dft(DFT_216,idft_in1,idft_out1,1);
dft(DFT_216,idft_in2,idft_out2,1);
break;
case 240:
dft(DFT_240,idft_in0,idft_out0,1);
dft(DFT_240,idft_in1,idft_out1,1);
dft(DFT_240,idft_in2,idft_out2,1);
break;
case 288:
dft(DFT_288,idft_in0,idft_out0,1);
dft(DFT_288,idft_in1,idft_out1,1);
dft(DFT_288,idft_in2,idft_out2,1);
break;
case 300:
dft(DFT_300,idft_in0,idft_out0,1);
dft(DFT_300,idft_in1,idft_out1,1);
dft(DFT_300,idft_in2,idft_out2,1);
break;
case 324:
dft(DFT_324,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_324,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_324,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 360:
dft(DFT_360,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_360,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_360,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 384:
dft(DFT_384,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_384,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_384,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 432:
dft(DFT_432,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_432,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_432,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 480:
dft(DFT_480,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_480,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_480,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 540:
dft(DFT_540,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_540,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_540,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 576:
dft(DFT_576,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_576,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_576,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 600:
dft(DFT_600,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_600,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_600,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 648:
dft(DFT_648,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_648,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_648,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 720:
dft(DFT_720,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_720,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_720,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 768:
dft(DFT_768,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_768,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_768,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 864:
dft(DFT_864,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_864,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_864,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 900:
dft(DFT_900,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_900,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_900,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 960:
dft(DFT_960,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_960,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_960,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 972:
dft(DFT_972,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_972,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_972,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 1080:
dft(DFT_1080,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_1080,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_1080,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 1152:
dft(DFT_1152,(int16_t *)idft_in0,(int16_t *)idft_out0,1);
dft(DFT_1152,(int16_t *)idft_in1,(int16_t *)idft_out1,1);
dft(DFT_1152,(int16_t *)idft_in2,(int16_t *)idft_out2,1);
break;
case 1200:
dft(DFT_1200,idft_in0,idft_out0,1);
dft(DFT_1200,idft_in1,idft_out1,1);
dft(DFT_1200,idft_in2,idft_out2,1);
break;
default:
// should not be reached
LOG_E( PHY, "Unsupported Msc_PUSCH value of %"PRIu16"\n", Msc_PUSCH );
return;
dft(dftsize, idft_in0, idft_out0, 1);
dft(dftsize, idft_in1, idft_out1, 1);
dft(dftsize, idft_in2, idft_out2, 1);
}
for (i=0,ip=0; i<Msc_PUSCH; i++,ip+=4) {
@@ -391,9 +193,6 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) {
((simde__m128i *)z11)[i]=simde_mm_sign_epi16(((simde__m128i *)z11)[i],*(simde__m128i *)&conjugate2[0]);
}
}
simde_mm_empty();
simde_m_empty();
}

Some files were not shown because too many files have changed in this diff Show More